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公开(公告)号：US20210343242A1
公开(公告)日：2021-11-04
申请号：US17243915
申请日：2021-04-29
发明人： Zhichong WANG , Fuqiang LI , Peng LIU , Xinglong LUAN , Jing FENG
IPC分类号： G09G3/3258 , G09G3/3291 , H01L27/32
摘要： A pixel circuit includes a data writing sub-circuit, a light-emitting control sub-circuit and a driving sub-circuit. The data writing sub-circuit is connected to the driving sub-circuit, and is configured to write a data voltage signal into the driving sub-circuit and compensate it, in response to a first gate signal and a second gate signal. The light-emitting control sub-circuit is connected to the driving sub-circuit, and is configured to close a line between a first power supply voltage terminal and a second power supply voltage terminal, in response to a first enable signal and a second enable signal. The driving sub-circuit is configured to provide a driving current to a light-emitting device through the closed line according to the written data voltage signal. Phases of the first enable signal and the first gate signal are opposite, and phases of the second enable signal and the second gate signal are opposite.
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32.发明申请公开(公告)号：US20200273419A1
公开(公告)日：2020-08-27
申请号：US16461818
申请日：2018-11-05
IPC分类号： G09G3/36
摘要： A shift register unit and a driving method, a grid driving circuit and a display device are disclosed. A shift register unit includes an input circuit, a first reset circuit, and an output circuit. The input circuit includes an input terminal configured to perform a first control on the first control node and the first node in response to an input signal of the input terminal, and then perform a second control on the first node under the control of the level of the first node, the first node is located in a path where the input signal incurs the first control; the first reset circuit is configured to reset the first control node in response to the first reset signal; the output circuit is configured to output an output signal to an output terminal under the control of the level of the first control node.
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公开(公告)号：US20200243013A1
公开(公告)日：2020-07-30
申请号：US16600908
申请日：2019-10-14
发明人： Zhichong WANG , Fuqiang LI , Jing FENG , Peng LIU , Xinglong LUAN
IPC分类号： G09G3/3258
摘要： Disclosed are a pixel circuitry, a method for driving the same and a display device. The pixel circuitry includes a light-emitting element, a driving circuit, a compensation control circuit, an initialization circuit, an energy storage circuit, a writing control circuit and a light-emitting control circuit. The driving circuit is configured to drive the light-emitting element to emit light. The initialization circuit is configured to write an initialization voltage to a control end of the driving circuit to control the driving circuit to be turned on or off. The compensation control circuit is configured to turn on the driving circuit and perform threshold voltage compensation on the driving circuit. The writing control circuit is configured to write a data voltage inputted by a data line to a second end of the energy storage circuit and write a reference voltage to the second end of the energy storage circuit.
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34.发明申请公开(公告)号：US20190304559A1
公开(公告)日：2019-10-03
申请号：US16158735
申请日：2018-10-12
发明人： Zhichong WANG
摘要： A shift register unit, a method of driving a shift register unit, a gate driving circuit and a display device are provided. The shift register unit includes an input circuit, a first pull-up node reset circuit and an output circuit. The input circuit is configured to control an level of a pull-up node to a first level in response to an input signal of an input terminal, and thereafter control a level of a first node to a second level under control of a level of a pull-down node. The first node is in a current path for controlling the level of the pull-up node. The first pull-up node reset circuit is configured to reset the pull-up node in response to a first reset signal. The output circuit is configured to output a clock signal to an output terminal under control of the level of the pull-up node.
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公开(公告)号：US20190279588A1
公开(公告)日：2019-09-12
申请号：US16066827
申请日：2017-12-14
发明人： Jiha KIM , Lijun YUAN , Zhichong WANG , Mingfu HAN , Xing YAO , Guangliang SHANG , Seung Woo HAN , Yun Sik IM , Jing LV , Yinglong HUANG , Jung Mok JUN , Haoliang ZHENG
摘要： There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.
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36.发明申请公开(公告)号：US20190027079A1
公开(公告)日：2019-01-24
申请号：US15577402
申请日：2017-05-03
发明人： Guangliang SHANG , Xing YAO , Mingfu HAN , Seung-Woo HAN , Yun-Sik IM , Jing LV , Yinglong HUANG , Jung-Mok JUN , Xue DONG , Haoliang ZHENG , Lijun YUAN , Zhichong WANG , Ji Ha KIM
摘要： A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.
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37.发明申请公开(公告)号：US20180108289A1
公开(公告)日：2018-04-19
申请号：US15502983
申请日：2016-05-19
发明人： Haoliang ZHENG , Seungwoo HAN , Guangliang SHANG , Hyunsic CHOI , Mingfu HAN , Xing YAO , Zhichong WANG , Lijun YUAN
CPC分类号： G09G3/2092 , G09G3/20 , G09G2300/0408 , G09G2300/0871 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/02 , G11C19/28
摘要： The present disclosure relates to a shift register unit and driving method thereof, a gate driving circuit and a display device. The shift register unit comprises: an input module for controlling a level of a first node based on a scan pulse, an output module for controlling a scan pulse output based on the level of the first node, a reset module for resetting the first node and the scan pulse output, and a control module for generating a reset trigger signal, wherein the reset module further resets the first node based on the reset trigger signal. The shift register units can be cascaded to form a gate driving circuit to realize output of multiple scan pulses. By integrating such a gate driving circuit on the array substrate, area of the bezel region of the array substrate can be reduced, thereby facilitating bezel narrowing of a display device. At the same time, due to presence of the control module, the reset module is enabled to reset the first node more stably while normal output of the scan pulse is maintained.
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