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公开(公告)号：US20200273419A1
公开(公告)日：2020-08-27
申请号：US16461818
申请日：2018-11-05
IPC分类号： G09G3/36
摘要： A shift register unit and a driving method, a grid driving circuit and a display device are disclosed. A shift register unit includes an input circuit, a first reset circuit, and an output circuit. The input circuit includes an input terminal configured to perform a first control on the first control node and the first node in response to an input signal of the input terminal, and then perform a second control on the first node under the control of the level of the first node, the first node is located in a path where the input signal incurs the first control; the first reset circuit is configured to reset the first control node in response to the first reset signal; the output circuit is configured to output an output signal to an output terminal under the control of the level of the first control node.
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公开(公告)号：US20240321197A1
公开(公告)日：2024-09-26
申请号：US18027376
申请日：2022-05-12
发明人： Guangliang SHANG , Jiangnan LU , Li WANG , Mengyang WEN , Xing YAO , Libin LIU
IPC分类号： G09G3/3233 , G09G3/3266 , G09G3/3275
CPC分类号： G09G3/3233 , G09G3/3266 , G09G3/3275 , G09G2310/08 , G09G2320/0247 , G09G2330/021
摘要： Provided is a display substrate, a drive method thereof and a display apparatus, the display substrate includes: a first drive mode and a second drive mode, the first drive mode has a refresh rate less than that of the second drive mode, wherein the contents displayed on the display substrate include a plurality of display frames, in the first drive mode, the display frames include: a refresh frame and at least one maintain frame; the display substrate includes pixel circuits arranged in an array, the pixel circuits include a data signal line and a first initial signal line; the data signal line provides a first data signal in the maintain frame, the voltage value of the first data signal is constant, and/or the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, the first initial signal is an AC signal.
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公开(公告)号：US20240290271A1
公开(公告)日：2024-08-29
申请号：US18044967
申请日：2022-06-29
发明人： Zhenzhen SHAN , Jiangnan LU , Guangliang SHANG , Libin LIU , Jianchao ZHU , Xing YAO
IPC分类号： G09G3/3258
CPC分类号： G09G3/3258 , G09G2300/0426
摘要： A display substrate includes a driving module arranged on the base substrate, the driving module includes a plurality of driving units, and the driving unit includes a plurality of stages of driving circuits; the driving unit includes a first signal line, and the driving circuit includes an output sub-circuit; the display substrate includes at least two metal layers stacked along a direction away from the base substrate; in at least one driving unit, an orthographic projection of the first signal line on the base substrate at least partially overlaps an orthographic projection of a first electrode or a second electrode of at least one transistor included in the output sub-circuit on the base substrate, the first electrode and the second electrode are arranged on the same metal layer, and the first electrode and the first signal line are arranged on different metal layers.
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公开(公告)号：US20230351970A1
公开(公告)日：2023-11-02
申请号：US17636898
申请日：2021-03-24
发明人： Jiangnan LU , Guangliang SHANG , Libin LIU , Li WANG , Xinshe YIN , Shiming SHI
IPC分类号： G09G3/3266
CPC分类号： G09G3/3266 , G09G2310/0286 , G11C19/28
摘要： Provided is a display substrate including a display region and a non-display region. The non-display region is provided with a gate drive circuit, and the gate drive circuit includes a plurality of cascaded shift register units; a shift register unit includes an input sub-circuit and a denoising output sub-circuit. The denoising output sub-circuit is connected with the input sub-circuit, a first group of clock signal lines, and a second group of clock signal lines, and the input sub-circuit is connected with a third group of clock signal lines. The third group of clock signal lines, the input sub-circuit, the first group of clock signal lines, the denoising output sub-circuit, and the second group of clock signal lines are sequentially arranged along a first direction.
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公开(公告)号：US20230178046A1
公开(公告)日：2023-06-08
申请号：US17921082
申请日：2021-05-12
发明人： Guangliang SHANG , Tian DONG , Shuo HUANG , Can ZHENG
IPC分类号： G09G3/36
CPC分类号： G09G3/3674 , G09G2310/0286
摘要： A driving method and device for a shift register. In a data refreshing phase, loading an input signal having a pulse level to an input signal end, loading a control clock pulse signal to a control clock signal end, loading a noise reduction clock pulse signal to a noise reduction clock signal end, controlling a cascade signal end of the shift register to output a cascade signal having a pulse level, and controlling a drive signal end of the shift register to output a drive signal having a pulse level; in a data holding phase, loading a fixed voltage signal to the input signal end, loading a first set signal to the control clock signal end, loading a second set signal to the noise reduction clock signal end, controlling the cascade signal end to output a fixed voltage signal having a second level.
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公开(公告)号：US20220343855A1
公开(公告)日：2022-10-27
申请号：US17433668
申请日：2021-02-24
发明人： Guangliang SHANG , Tian DONG , Xinshe YIN , Mei LI , Libin LIU , Shiming SHI
IPC分类号： G09G3/3266 , G11C19/28
摘要： Provided are a gate driving circuit, a display substrate, a display device and a gate driving method, the gate driving circuit includes: a frequency doubling control circuit and an effective output circuit including first shift registers, the first shift register at the first stage has a first signal input terminal coupled with an output control signal line and a second signal input terminal coupled with the frequency doubling control circuit; the frequency doubling control circuit is coupled to the output control signal line, for providing a frequency doubling control signal thereto after a preset time period from the receipt of the output control signal in response to an output control signal from the output control signal line; the first shift register at the first stage outputs a scanning signal in response to the output control signal and a scanning signal in response to the frequency doubling control signal.
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公开(公告)号：US20210407563A1
公开(公告)日：2021-12-30
申请号：US16767755
申请日：2019-07-02
发明人： Guangliang SHANG , Xinshe YIN , Qian YANG , Libin LIU , Shiming SHI , Dawei WANG
摘要： Embodiments of the present disclosure disclose a shift register unit, a driving method thereof, and a device. The shift register unit includes an input circuit, a node control circuit, a first control output circuit, a second control output circuit and an output circuit. By providing the first control output circuit and the second control output circuit, the first control output circuit and the second control output circuit may operate alternately, so that the first control output circuit and the second control output circuit may have time for characteristics recovery respectively, thus improving the service life and output stability of the shift register unit.
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8.发明申请公开(公告)号：US20200219576A1
公开(公告)日：2020-07-09
申请号：US16697889
申请日：2019-11-27
发明人： Xing YAO , Mingfu HAN , Guangliang SHANG , Haoliang ZHENG , Lijun YUAN , Zhenyu ZHANG
摘要： A shift register unit and a method for driving the same, a gate drive circuitry and a display device are provided. The shift register unit includes: an output circuit, coupled to a first signal output terminal and a pull-up control node, and configured to receive a first clock signal and output the first clock signal to the first signal output terminal under control of a potential of the pull-up control node; an output control circuit, coupled to a signal input terminal, the pull-up control node and the first signal output terminal; a clock control circuit configured to receive a first clock signal and at least one additional clock signal and generate a second clock signal using the first clock signal and the at least one additional clock signal; and a transmission circuit coupled to a second signal output terminal and the pull-up control node.
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公开(公告)号：US20200082757A1
公开(公告)日：2020-03-12
申请号：US16399612
申请日：2019-04-30
发明人： Lijun YUAN , Guangliang SHANG , Xing YAO , Haoliang ZHENG , Mingfu HAN
IPC分类号： G09G3/3258 , G09G3/3233 , G09G3/3291 , G09G3/3266 , H01L27/32
摘要： The present disclosure provides a pixel driving circuit and a method for driving the same, a pixel unit, and a display panel. The pixel circuit includes: a driving sub-circuit, configured to generate driving current based on a data signal and a first voltage; a first light-emitting control sub-circuit configured to receive a first control signal and the first voltage, and provide the first voltage to the driving sub-circuit under control of the first control signal; a second light-emitting control sub-circuit configured to receive a second control signal and provide driving current generated by the driving sub-circuit to an output terminal of the pixel driving circuit under control of the second control signal; a driving control sub-circuit configured to receive the second control signal and the data signal and provide the data signal to the driving sub-circuit under control of the second control signal; and a reset sub-circuit configured to receive a reset signal and a second voltage, and reset the driving sub-circuit using the second voltage under control of the reset signal.
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公开(公告)号：US20190057638A1
公开(公告)日：2019-02-21
申请号：US15768948
申请日：2017-10-17
发明人： Jiha KIM , Seung Woo HAN , Guangliang SHANG , Xing YAO , Haoliang ZHENG , Mingfu HAN , Zhichong WANG , Lijun YUAN , Yun Sik IM , Jing LV , Yinglong HUANG , Xue DONG
摘要： A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.
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