公开(公告)号：US20220335889A1

公开(公告)日：2022-10-20

申请号：US17760733

申请日：2021-03-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang ZHENG ,  Minghua XUAN ,  Dongni LIU ,  Zhenyu ZHANG ,  Li XIAO ,  Liang CHEN ,  Hao CHEN ,  Jiao ZHAO ,  Lijun YUAN ,  Yi OUYANG ,  Qi QI

IPC: G09G3/3233 ,  G11C19/28

Abstract: A shift register (SR) includes a voltage control circuit (110) and a bias compensation circuit (120). The voltage control circuit (110) is configured to control a voltage at a first node (Output) to be a first voltage or a second voltage. The bias compensation circuit (120) is configured to: when the voltage at the first node (Output) is the first voltage, transmit a first signal received by a first signal terminal (VDD-A) to a first signal output terminal (EM1), and transmit a second signal received by a second signal terminal (VDD-B) to a second signal output terminal (EM2); and in response to the voltage at the first node (Output) being the second voltage, transmit a signal received by a first voltage terminal (LVGL1) to the first signal output terminal (EM1) and the second signal output terminal (EM2).

公开(公告)号：US20210193027A1

公开(公告)日：2021-06-24

申请号：US17086097

申请日：2020-10-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang ZHENG ,  Dongni LIU ,  Minghua XUAN ,  Zhenyu ZHANG ,  Li XIAO ,  Liang CHEN ,  Hao CHEN ,  Guangliang SHANG ,  Lijun YUAN ,  Xing YAO

IPC: G09G3/32

Abstract: A shift register includes an input sub-circuit, a control sub-circuit, an output sub-circuit and a reset sub-circuit. The input sub-circuit is configured to transmit an input signal from an input signal terminal to a pull-up node. The control sub-circuit is configured to transmit a clock signal from a clock signal terminal to the control node. The output sub-circuit is configured to transmit a second voltage signal from a second voltage signal terminal to a first output signal terminal, and to transmit a first voltage signal from a first voltage signal terminal to the first output signal terminal. The reset sub-circuit is configured to transmit the second voltage signal to the control node to reset the control node, and to transmit a third voltage signal from the third voltage signal terminal to the pull-up node to reset the pull-up node.

公开(公告)号：US20210166601A1

公开(公告)日：2021-06-03

申请号：US17044148

申请日：2020-03-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang SHANG ,  Lijun YUAN ,  Haoliang ZHENG ,  Libin LIU ,  XING YAO ,  Seungwoo HAN

IPC: G09G3/20

Abstract: The present disclosure provides a gate driving unit, a gate driving method, a gate driving circuitry and a display device. The gate driving unit includes a reverse-phase gate driving signal output end, a normal-phase gate driving signal output end, an input circuitry, an output control circuitry, an input node control circuitry and an output circuitry. The input circuitry is configured to control an input end to be electrically connected to an input node under the control of a first clock signal. The output control circuitry is configured to control a potential at an output node under the control of a potential at the input node and a second clock signal. The input node control circuitry is configured to control the potential at the input node in accordance with the potential at the output node under the control of the second clock signal. The output circuitry is configured to output a reverse-phase gate driving signal and output a normal-phase gate driving signal in accordance with the potential at the output node.

公开(公告)号：US20200219428A1

公开(公告)日：2020-07-09

申请号：US16515880

申请日：2019-07-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lijun YUAN ,  Xing YAO ,  Guangliang SHANG ,  Haoliang ZHENG ,  Zhenyu ZHANG

IPC: G09G3/20 ,  G11C19/28

Abstract: A shift register circuit according to an embodiment of the present disclosure includes an input sub-circuit and N-stage output sub-circuits. The input sub-circuit is configured to transmit an input signal to a pull up node at a first stage. The output sub-circuit at each stage is configured to transmit a clock signal from a clock signal terminal at a same stage to an output signal terminal at the same stage under the control of a pull-up node at the same stage. The output sub-circuit at each stage is further configured to transmit a signal transmitted to an output signal terminal at the same stage to a pull-up node at an immediately subsequent stage under the control of a shift control signal from a shift control signal terminal at the same stage.

公开(公告)号：US20200160768A1

公开(公告)日：2020-05-21

申请号：US16399510

申请日：2019-04-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Donghui WANG ,  Hong WANG ,  Lijun YUAN ,  Yanhui XI ,  Haoliang ZHENG ,  Yuxin BI

IPC: G09G3/20

Abstract: The present disclosure discloses a source driving circuit and a display panel. The source driving circuit includes a plurality of driving sub-circuits, and each of the plurality of driving sub-circuits includes: a driver, including a plurality of source channels; a plurality of switches, first terminals of the plurality of switches are electrically connected to a plurality of data lines of a display panel in one-to-one correspondence, wherein each of the plurality of source channels is electrically connected to second terminals of at least two of the plurality of switches; and a control line, electrically connected to control terminals of the plurality of switches. Sub-pixels corresponding to data lines that are electrically connected to a same source channel through the switches have the same polarity and the same color.

公开(公告)号：US20220406243A1

公开(公告)日：2022-12-22

申请号：US17418808

申请日：2020-12-28

Applicant: Beijing BOE Display Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Ning CONG ,  Minghua XUAN ,  Can ZHANG ,  Ming YANG ,  Can WANG ,  Lijun YUAN

IPC: G09G3/32 ,  G09G3/3233

Abstract: The present disclosure provides a pixel circuit, a method for driving the same, a display substrate, and a display device, which belong to the field of display technologies. The pixel circuit includes a compensating circuit which can adjust an electric potential of a second control node (a gate of a transistor controlling conduction or non-conduction between a first connection node and a second connection node) based on an electric potential of a first control node, and adjust an electric potential of the second control node based on an electric potential of the second connection node. When the pixel circuit is driven, electric potential of each control signal can be controlled, such that influence of a threshold voltage of a transistor on an electric potential finally output to the second control node is relatively small, that is, influence of drifting of a threshold voltage on display uniformity is reduced. The display device according to the present disclosure achieves a good display effect.

公开(公告)号：US20210358381A1

公开(公告)日：2021-11-18

申请号：US16336546

申请日：2018-08-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhichong WANG ,  Haoliang ZHENG ,  Seungwoo HAN ,  Guangliang SHANG ,  Lijun YUAN ,  Xing YAO ,  Mingfu HAN

IPC: G09G3/20

Abstract: Disclosed is a shift register unit, including a first input circuit, an input control circuit, a pull-down control circuit, a pull-down circuit, an output circuit and a second input circuit. The first input circuit includes a first input sub-circuit, and is configured to, under control of the first signal input terminal, cause a voltage of the first voltage terminal to be output to a second terminal of the first input sub-circuit and output to the pull-up node via a first terminal thereof. The input control circuit is configured to pull down a potential of the second terminal to the potential of a first power supply voltage terminal under control of an enable signal terminal.

公开(公告)号：US20210225312A1

公开(公告)日：2021-07-22

申请号：US16307060

申请日：2018-06-07

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Mingfu HAN ,  Guangliang SHANG ,  Seung Woo HAN ,  Xing YAO ,  Haoliang ZHENG ,  Lijun YUAN ,  Zhichong WANG

IPC: G09G3/36 ,  G11C19/28

Abstract: A shift register unit and a drive method thereof, a gate driving circuit and a display device are provided. The shift register unit includes an input circuit, a pull-up node reset circuit, an output circuit and a coupling circuit. The input circuit is configured to charge a pull-up node in response to an input signal; the pull-up node reset circuit is configured to reset the pull-up node in response to a reset signal; the output circuit is configured to output a first clock signal to a first output terminal under control of a level of the pull-up node; and the coupling circuit is configured to control, by coupling, a potential of the pull-up node in response to a second clock signal.

公开(公告)号：US20210217353A1

公开(公告)日：2021-07-15

申请号：US16976858

申请日：2019-11-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiao ZHAO ,  Li XIAO ,  Minghua XUAN ,  Haoliang ZHENG ,  Dongni LIU ,  Jing LIU ,  Qi QI ,  Zhenyu ZHANG ,  Liang CHEN ,  Hao CHEN ,  Lijun YUAN

IPC: G09G3/32 ,  G11C19/28 ,  H01L25/075 ,  H01L27/02 ,  H01L27/12 ,  H01L33/62

Abstract: An array substrate has a display area, and the array substrate includes at least one pixel group and at least one pixel circuit group. The at least one pixel group is disposed in the display area, and each pixel group includes a plurality of pixels arranged in an array. Each pixel circuit group is disposed between two adjacent rows of pixels or two adjacent columns of pixels in a corresponding pixel group.

公开(公告)号：US20210027699A1

公开(公告)日：2021-01-28

申请号：US16904585

申请日：2020-06-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Haoliang ZHENG ,  Minghua XUAN ,  Dongni LIU ,  Ning CONG ,  Zhenyu ZHANG ,  Lijun YUAN ,  Yi OUYANG ,  Guangliang SHANG

IPC: G09G3/32

Abstract: Disclosed are a display panel and a display device. The display panel includes M rows and N columns of pixel units. The display panel is divided into R regions along a column direction, and an i-th region includes: (1+M(i−1)/R)-th row to a (Mi/R)-th row of pixel units. The display panel further includes M shift registers, M light emitting drivers, R light emitting control scan staring signal terminals, R scan start signal terminals for controlling time length and R scan start signal terminals for controlling current. An i-th row of pixel units is connected with an i-th shift register and an i-th light emitting driver, a light emitting driver connected to a first row of pixel units in the i-th region is connected with an i-th scan start signal terminal for controlling light emission.