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公开(公告)号：US20100125750A1
公开(公告)日：2010-05-20
申请号：US12273155
申请日：2008-11-18
IPC分类号： G06F11/20
CPC分类号： G06F11/0793 , G06F11/073 , G06F12/0802
摘要： A data processing system and method of operation has a processor coupled to a cache. Cache control circuitry is coupled to the cache and performs error detection. A user programmable error action control register stores a control value for selecting a type of error action to be taken when a cache error is detected. A first value of the control value permits handling of a cache error that is transparent to the processor, and a second value permits handling of the cache error by taking an exception that is visible to the processor. Various alternate actions to a detected error, including error correction or cache line invalidation, may be taken in response to other values of the control value.
摘要翻译： 数据处理系统和操作方法具有耦合到高速缓存的处理器。 缓存控制电路耦合到高速缓存并执行错误检测。 用户可编程错误动作控制寄存器存储用于选择检测到高速缓存错误时要采取的错误动作的类型的控制值。 控制值的第一个值允许处理对处理器透明的高速缓存错误，第二个值允许通过处理器可见的异常来处理高速缓存错误。 响应于控制值的其他值，可以采取针对检测到的错误的各种替代动作，包括纠错或高速缓存线无效。
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32.发明授权Instruction for conditionally yielding to a ready thread based on priority criteria 有权根据优先级标准有条件地屈服于准备好的线程的指令公开(公告)号：US07584344B2
公开(公告)日：2009-09-01
申请号：US11381284
申请日：2006-05-02
IPC分类号： G06F9/40
CPC分类号： G06F9/4843 , G06F2209/507
摘要： An integrated circuit (10) has a conditional yield instruction (305) which may be used to conditionally yield execution of a currently active thread based on priority and status of other threads. In one embodiment, an I bit 304 may be used to designate whether the priority selection bits (50) are stored in the instruction itself. If the priority selection bits (50) are not stored in the instruction itself, a portion of the instruction (302) may be used to store a location indicator which indicates where the priority selection bits (50) are located (e.g. register file 22).
摘要翻译： 集成电路（10）具有条件收益率指令（305），其可以用于基于其他线程的优先级和状态有条件地产生当前活动线程的执行。 在一个实施例中，可以使用I比特304来指示优先权选择比特（50）是否被存储在指令本身中。 如果优先级选择位（50）未被存储在指令本身中，则指令（302）的一部分可以用于存储指示优先级选择位（50）所在位置的位置指示符（例如寄存器文件22） 。
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公开(公告)号：US09152587B2
公开(公告)日：2015-10-06
申请号：US13485120
申请日：2012-05-31
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned interrupt controller (14) can determine if the delay command can be performed based on local access control information.
摘要翻译： 一种用于数据处理系统的方法和电路，通过执行控制指令来编码和存储具有硬件的数据有效载荷中的延迟命令（例如，DEFER或SUSPEND）来提供具有用于处理分区中断请求的有效延迟机制的分区中断控制器 - 插入分区属性（LPID），用于存储到从专用寄存器（46）检索的物理地址（PA）处的命令寄存器（25），使得分区中断控制器（14）可以确定是否可以执行延迟命令 基于本地访问控制信息。
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34.发明申请Processor Interrupt Interface with Interrupt Partitioning and Virtualization Enhancements 有权具有中断分区和虚拟化增强功能的处理器中断接口公开(公告)号：US20140047150A1
公开(公告)日：2014-02-13
申请号：US13570874
申请日：2012-08-09
IPC分类号： G06F13/26
CPC分类号： G06F13/26 , G06F9/45533 , G06F9/5077 , G06F13/14 , G06F13/24
摘要： A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.
摘要翻译： 用于数据处理系统（200）的方法和电路通过将所接收的中断请求相关联的中断标识符，分区标识符，线程标识符和优先级级别存储在位于专用寄存器（35-38）中来提供基于处理器的分区优先级阻塞机制 在处理器核心（26）上，以便在分区的基础上实现快速有效的中断优先级阻塞。
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公开(公告)号：US08095831B2
公开(公告)日：2012-01-10
申请号：US12273155
申请日：2008-11-18
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/073 , G06F12/0802
摘要： A data processing system and method of operation has a processor coupled to a cache. Cache control circuitry is coupled to the cache and performs error detection. A user programmable error action control register stores a control value for selecting a type of error action to be taken when a cache error is detected. A first value of the control value permits handling of a cache error that is transparent to the processor, and a second value permits handling of the cache error by taking an exception that is visible to the processor. Various alternate actions to a detected error, including error correction or cache line invalidation, may be taken in response to other values of the control value.
摘要翻译： 数据处理系统和操作方法具有耦合到高速缓存的处理器。 缓存控制电路耦合到高速缓存并执行错误检测。 用户可编程错误动作控制寄存器存储用于选择检测到高速缓存错误时要采取的错误动作的类型的控制值。 控制值的第一个值允许处理对处理器透明的高速缓存错误，第二个值允许通过处理器可见的异常来处理高速缓存错误。 响应于控制值的其他值，可以采取针对检测到的错误的各种替代动作，包括纠错或高速缓存线无效。
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36.发明授权Microprocessor having a content addressable memory (CAM) device as a functional unit therein and method of operation 有权具有内容可寻址存储器（CAM）装置作为功能单元的微处理器及其操作方法公开(公告)号：US06792502B1
公开(公告)日：2004-09-14
申请号：US09689028
申请日：2000-10-12
IPC分类号： G06F1200
CPC分类号： G06F9/3885 , G11C15/00
摘要： A microprocessor architecture (310) has a plurality of functional units arranged in a parallel manner between one or more source buses (412 and/or 414) and one or more result buses (490). At least one of the functional units within the architecture is a content addressable memory (CAM) functional unit (430) which can be issued CPU instructions via a sequencer (480) much like any other functional unit. The operation of the CAM (430) may be pipelined in one or more stages so that the CAM's throughput may be increased to accommodate the higher clock rates that are likely used within the architecture (310). One embodiment involves pipelining the CAM operation in three stages (510, 520, and 530) in order to sequentially perform data input and precharge operations, followed by match operations, and followed Finally by priority encoding and data output.
摘要翻译： 微处理器架构（310）具有在一个或多个源总线（412和/或414）与一个或多个结果总线（490）之间并行布置的多个功能单元。 架构内的功能单元中的至少一个是内容可寻址存储器（CAM）功能单元（430），其可以与任何其他功能单元类似地经由定序器（480）发出CPU指令。 CAM（430）的操作可以在一个或多个阶段中流水线化，使得可以增加CAM的吞吐量以适应架构（310）中可能使用的较高时钟速率。 一个实施例涉及以三个阶段（510,520和530）流水线CAM操作，以便顺序执行数据输入和预充电操作，随后进行匹配操作，随后最后通过优先编码和数据输出。
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37.发明授权Interrupt priority management using partition-based priority blocking processor registers 有权使用基于分区的优先级阻塞处理器寄存器进行中断优先级管理公开(公告)号：US09442870B2
公开(公告)日：2016-09-13
申请号：US13570843
申请日：2012-08-09
CPC分类号： G06F13/26 , G06F9/45533 , G06F9/5077 , G06F13/14 , G06F13/24
摘要： A method and circuit for a data processing system (20) provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers (27-29) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.
摘要翻译： 一种用于数据处理系统（20）的方法和电路通过在位于处理器核心（26）的专用寄存器（27-29）中存储优先级和相关分区信息来提供基于处理器的分区优先级阻塞机制，以实现快速和 基于分区的高效中断优先级阻塞。
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38.发明申请Interrupt Priority Management Using Partition-Based Priority Blocking Processor Registers 有权使用基于分区的优先级阻塞处理器寄存器进行中断优先级管理公开(公告)号：US20140047149A1
公开(公告)日：2014-02-13
申请号：US13570843
申请日：2012-08-09
IPC分类号： G06F13/26
CPC分类号： G06F13/26 , G06F9/45533 , G06F9/5077 , G06F13/14 , G06F13/24
摘要： A method and circuit for a data processing system (20) provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers (27-29) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.
摘要翻译： 一种用于数据处理系统（20）的方法和电路通过在位于处理器核心（26）的专用寄存器（27-29）中存储优先级和相关分区信息来提供基于处理器的分区优先级阻塞机制，以实现快速和 基于分区的高效中断优先级阻塞。
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公开(公告)号：US20130326102A1
公开(公告)日：2013-12-05
申请号：US13485120
申请日：2012-05-31
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned interrupt controller (14) can determine if the delay command can be performed based on local access control information.
摘要翻译： 一种用于数据处理系统的方法和电路，通过执行控制指令来编码和存储具有硬件的数据有效载荷中的延迟命令（例如，DEFER或SUSPEND）来提供具有用于处理分区中断请求的有效延迟机制的分区中断控制器 - 插入分区属性（LPID），用于存储到从专用寄存器（46）检索的物理地址（PA）处的命令寄存器（25），使得分区中断控制器（14）可以确定是否可以执行延迟命令 基于本地访问控制信息。
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公开(公告)号：US20130290585A1
公开(公告)日：2013-10-31
申请号：US13460287
申请日：2012-04-30
CPC分类号： G06F13/14
摘要： A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g., 14, 61) by executing a control instruction (47, 48) to encode and store an access command (CMD) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned device (14, 61) can determine if the access command can be performed based on local access control information.
摘要翻译： 用于数据处理系统的方法和电路通过执行控制指令（47,48）来提供用于访问分区设备（例如，14,61）的虚拟化指令，以将数据有效载荷中的访问命令（CMD）编码和存储在 硬件插入分区属性（LPID），用于存储到从专用寄存器（46）检索的物理地址（PA）处的命令寄存器（25），使得分区设备（14,61）可以确定访问命令是否可以 基于本地访问控制信息执行。
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