-
公开(公告)号：US20080079122A1
公开(公告)日：2008-04-03
申请号：US11540770
申请日：2006-09-29
IPC分类号： H01L23/58
CPC分类号： H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24′ of the second dopant type.
-
公开(公告)号：US07282386B2
公开(公告)日：2007-10-16
申请号：US11117996
申请日：2005-04-29
IPC分类号： H01L21/00
CPC分类号： H01L29/872 , H01L29/063 , H01L29/0692 , H01L29/66136 , H01L29/66143 , H01L29/8611
摘要： A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias voltage condition.
摘要翻译： 肖特基器件具有多个单元电池，每个单元电池具有肖特基接触部分，由反向偏置电压条件期间相对于器件的表面在垂直和水平方向上形成耗尽区域的端接结构包围。
-
公开(公告)号：US06573562B2
公开(公告)日：2003-06-03
申请号：US10004186
申请日：2001-10-31
IPC分类号： H01L2976
CPC分类号： H03K17/08 , H01L21/761 , H01L27/0629 , H01L27/0635 , H01L27/0664 , H01L27/0676 , H01L27/0814 , H01L29/1083 , H01L29/1087 , H01L29/7835 , H01L29/8611 , H01L29/866
摘要： A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350, 650, 850). The transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the first conductivity type (ii) a terminal, which includes a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region, and (iii) a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate. The switching circuit is electrically coupled to the third doped region to adjust the bias of the third doped region.
摘要翻译： 半导体元件包括具有第一导电类型的第一和第二部分（111,112）的半导体衬底（110），至少部分地位于半导体衬底中的晶体管（120）和开关电路（150,350,650 ，850）。 晶体管包括（i）半导体衬底的第一部分中的第一掺杂区域，并具有第一导电类型（ii）端子，其包括具有第二导电类型并位于半导体的第一部分中的第二掺杂区域 衬底并且在第一掺杂区域上方，以及（iii）具有第二导电类型并且位于半导体衬底的第一部分下方并位于半导体衬底的第二部分之下的第三掺杂区域。 开关电路电耦合到第三掺杂区域以调节第三掺杂区域的偏置。
-
公开(公告)号：US06528849B1
公开(公告)日：2003-03-04
申请号：US09652813
申请日：2000-08-31
IPC分类号： H01L2978
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/7393 , H01L29/7831
摘要： A MOSFET includes a source region, a first channel region proximate to the source region, a first gate region adjacent to the first base region, a drain region, a second channel region proximate to the drain region, and a second gate region adjacent to the second channel region. A first channel is formed within the first channel region in dependence upon a first voltage applied to the first gate region with respect to at least a first portion of the source region, and a second channel is formed within the second channel region in dependence upon a second voltage applied to the second gate region with respect to at least a second portion of the drain region. The MOSFET further includes a drift region coupled between the first channel region and the second channel region, where the drift region includes a set of alternating columns, each of which is also coupled between the first base region and the second base region. The set of alternating columns includes a plurality of columns doped with N− type impurities alternating with a plurality columns doped with P− type impurities.
摘要翻译： MOSFET包括源极区域，靠近源极区域的第一沟道区域，与第一基极区域相邻的第一栅极区域，漏极区域，靠近漏极区域的第二沟道区域以及与漏极区域相邻的第二栅极区域 第二通道区域。 根据相对于源区域的至少第一部分施加到第一栅极区域的第一电压，在第一沟道区域内形成第一沟道，并且第二沟道形成在第二沟道区内，依赖于 相对于漏极区域的至少第二部分施加到第二栅极区域的第二电压。 MOSFET还包括耦合在第一沟道区域和第二沟道区域之间的漂移区域，其中漂移区域包括一组交替的列，其中每一个也耦合在第一基极区域和第二基极区域之间。 这组交替的列包括掺杂有多个掺杂有P-型杂质的列的N型杂质的多个列。
-
35.发明授权MOSFET device including a source with alternating P-type and N-type regions 有权MOSFET器件包括具有交替P型和N型区的源公开(公告)号：US07851889B2
公开(公告)日：2010-12-14
申请号：US11742363
申请日：2007-04-30
IPC分类号： H01L21/00
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/1087 , H01L29/456 , H01L29/7835
摘要： Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well. An area (510) comprising regions of alternating conductivities is then formed in the semiconductor well.
摘要翻译： 提供了用于制造具有降低的双极效应的半导体器件的装置和方法。 一种装置包括半导体本体（120），其包括位于半导体本体附近的表面和晶体管源（300），并且晶体管源包括交替导电区域（3110,3120）的区域（310）。 另一种装置包括：半导体本体（120），其包括位于半导体本体中的第一导电性和晶体管源（500）。 晶体管源包括包括第二导电性的多个区域（5120），其中所述区域和半导体主体形成第一和第二电导率的交替区域的区域（510）。 一种方法包括在衬底（110）中注入包括第一导电性的半导体阱（120），并在半导体阱中注入包含第二导电性的多个掺杂区域（5120）。 然后在半导体阱中形成包括交变电导率区域的区域（510）。
-
公开(公告)号：US07791161B2
公开(公告)日：2010-09-07
申请号：US11213069
申请日：2005-08-25
申请人： Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
发明人： Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
IPC分类号： H01L29/00
CPC分类号： H01L29/0878 , H01L23/3677 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/66681 , H01L29/732 , H01L29/7816 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill. Significant area savings are also achieved.
摘要翻译： 为半导体器件提供了结构和方法。 这些器件包括填充有高掺杂多晶半导体的沟槽，其从表面延伸到器件的主体中，其中包括：（i）减少衬底电流注入，（ii）降低导通电阻和/或（iii）减少热 对基片的阻抗。 对于孤立的LDMOS器件，横向隔离壁（连接到源极）和掩埋层之间的电阻降低，从而降低衬底注入电流。 当放置在垂直装置的横向装置或收集器的漏极中时，多晶硅填充沟槽有效地放大了漏极或集电极区域，从而降低了导通电阻。 对于形成在氧化物隔离层上的器件，多晶填充沟槽期望地穿透该隔离层，从而改善从有源区到衬底的热传导。 多孔填充沟槽通过蚀刻和再填充方便地形成。 也实现了显着的面积节省。
-
公开(公告)号：US07763937B2
公开(公告)日：2010-07-27
申请号：US11601127
申请日：2006-11-15
IPC分类号： H01L29/00
CPC分类号： H01L29/063 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first region (70) a first PN junction (65) extending to the first surface (80), a contact region (68) of the second conductivity type in the second region (66) at the first surface (80) and spaced apart from the first PN junction (65) by a first distance (LDS), and a third region (82, 96-98, 108) of the first conductivity type and of a second length (LBR), underlying the second region (66) and forming a second PN junction (63) therewith spaced apart from the first surface (80) and located closer to the first PN junction (65) than to the contact region (68). The breakdown voltage is enhanced without degrading other useful properties of the device (60, 95, 100, 106).
摘要翻译： 为半导体器件（60,95,100,106）提供了方法和装置。 半导体器件（60,95,100,106）包括延伸到第一表面（80）的第一导电类型的第一区域（64,70），第二相对导电类型的第二区域（66） 与所述第一区域（70）形成延伸到所述第一表面（80）的第一PN结（65），在所述第一表面（80）处的所述第二区域（66）中的所述第二导电类型的接触区域（68） 与第一PN结（65）间隔开第一距离（LDS），以及第二导电类型和第二长度（LBR）的第三区域（82,96-98,108），位于第二区域 并且与第一表面（80）间隔开并且位于比接触区域（68）更靠近第一PN结（65）的位置处形成第二PN结（63）。 提高击穿电压，而不会降低器件（60,95,100,106）的其他有用特性。
-
公开(公告)号：US07436025B2
公开(公告)日：2008-10-14
申请号：US11540770
申请日：2006-09-29
IPC分类号： H01L29/76
CPC分类号： H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24′ of the second dopant type.
摘要翻译： 提供半导体器件10。 第一层12具有第一掺杂剂类型; 在第一层12上设置第二层14; 并且第三层16设置在第二层上并且具有第一掺杂剂类型。 多个第一和第二半导体区域22,24在第三层内。 第一半导体区域22具有第一掺杂剂类型，第二半导体区域24具有第二掺杂剂类型。 第一和第二半导体区域22,24以交替图案彼此横向地设置以形成超结，并且超结终止于第二掺杂剂类型的最终第二半导体区域24,24'。
-
公开(公告)号：US07329566B2
公开(公告)日：2008-02-12
申请号：US11142111
申请日：2005-05-31
申请人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
IPC分类号： H01L21/332 , H01L21/336
CPC分类号： H01L29/7393 , H01L29/66325
摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200) that includes a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130) having the second conductivity type located above at least a portion of the first semiconductor region, an emitter (150) having the second conductivity type disposed in the second semiconductor region, and a collector (170) having the second conductivity type disposed in the first semiconductor region. A sinker region (140) is provided to electrically tie the buried semiconductor region (115) to the second semiconductor region (130). In a particular embodiment, the second semiconductor region and the buried semiconductor region deplete the first semiconductor region in response to a reverse bias potential applied across the semiconductor component.
摘要翻译： 一种半导体元件和制造方法，包括绝缘栅双极晶体管（IGBT）（100,200），其包括具有第一导电类型的半导体衬底（110）和具有第二导电类型的掩埋半导体区域（115） 半导体衬底。 IGBT还包括具有位于掩埋半导体区域上方的第一导电类型的第一半导体区域（120），具有位于第一半导体区域的至少一部分上方的第二导电类型的第二半导体区域（130），发射极 150），并且具有设置在第一半导体区域中的具有第二导电类型的集电极（170）。 提供沉降片区域（140）以将掩埋的半导体区域（115）电连接到第二半导体区域（130）。 在特定实施例中，响应于施加在半导体部件上的反向偏置电位，第二半导体区域和掩埋半导体区域耗尽第一半导体区域。
-
公开(公告)号：US07095092B2
公开(公告)日：2006-08-22
申请号：US10836170
申请日：2004-04-30
IPC分类号： H01L29/00
CPC分类号： H01L29/7391 , H01L29/861
摘要： In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).
摘要翻译： 在一个实施例中，半导体器件10包括使用隔离区域（34,16和13）和多个掺杂剂浓度（30,20,24和26）的二极管，其可用于限制注入的寄生电流 进入半导体基板（12）。 可以使用隔离区域（34,16和13）上的各种偏压来影响半导体器件（10）的行为。 此外，可以形成覆盖在阳极（42）和阴极（40）之间的连接处的导电层（28）。 为了增加施加到阴极（40）的最大电压，该导电层（28）可以减小选定区域中的电场。
-
-
-
-
-
-
-
-
-
搜索结果
89 条记录 (耗时 0.029 秒)
