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112 条记录 (耗时 0.037 秒)

    Network processor for multiprotocol data flows
    34.
    发明授权
    Network processor for multiprotocol data flows 有权
    用于多协议数据流的网络处理器

    公开(公告)号：US06671280B1

    公开(公告)日：2003-12-30

    申请号：US09535794

    申请日：2000-03-29

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L1256

    CPC分类号： H04L49/30 ,  H04L45/502 ,  H04L49/201 ,  H04L49/251 ,  H04L49/3009 ,  H04L49/602 ,  H04L49/606 ,  H04L2012/5618 ,  H04L2012/5665

    摘要： A method for integrating Asynchronous Transfer Mode (ATM) and frame-based traffic flows within a telecommunications network is disclosed. The telecommunications network includes a network processor having upside processing means for delivering an incoming flow from the telecommunications network to a switch and downside processing means for delivering outgoing network traffic from the switch to the telecommunications network. The incoming flow is initially received at the upside processing means as a frame-based flow. The incoming flow may be characterized as belonging to a group having frame-based flows and ATM flows. In response to the receipt of the incoming flow, the incoming flow is determined if it is destined for a legacy, ATM-only device. The incoming flow is then processed according to the determined routing requirements and the incoming flow characterization before delivering the incoming flow to the switch.

    摘要翻译： 公开了一种在电信网络内集成异步传输模式（ATM）和基于帧的业务流的方法。 电信网络包括具有上行处理装置的网络处理器，用于将来自电信网络的输入流传送到交换机，以及下行处理装置，用于将来自交换机的输出网络业务传送到电信网络。 最初在上行处理装置处接收输入流作为基于帧的流。 输入流可以被表征为属于具有基于帧的流和ATM流的组。 响应于接收到的流入，确定进入流是否发往传统的仅ATM设备。 然后根据确定的路由要求和输入流特性，将传入流量传送到交换机之前处理进入流。

    Queue manager for a buffer
    35.
    发明授权
    Queue manager for a buffer 失效
    队列管理器为缓冲区

    公开(公告)号：US06557053B1

    公开(公告)日：2003-04-29

    申请号：US09477179

    申请日：2000-01-04

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

    IPC分类号： G06F1314

    CPC分类号： G06F13/1673

    摘要： A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

    摘要翻译： 提供了用于FIFO缓冲器的带宽保存队列管理器，优选地在ASIC芯片上，并且优选地包括分离的DRAM存储器，其维持FIFO队列，其可以超出FIFO缓冲器的数据存储空间，以根据需要提供附加的数据存储空间。 在ASIC芯片上使用FIFO缓冲器来存储和检索多个队列条目。 只要队列的总大小不超过缓冲区中可用的存储空间，则不需要额外的数据存储。 然而，当超过FIFO缓冲器中的一些预定量的缓冲存储空间时，数据被写入附加数据存储器并从其中读出，并且优选地是具有用于保持数据存储设备的峰值性能的最佳尺寸的数据包，以及哪个 被写入数据存储设备，使得它们以先入先出（FIFO）地址序列排队。 优选地，以突发模式将数据写入DRAM并从DRAM读取。

    Software management tree implementation for a network processor
    37.
    发明授权
    Software management tree implementation for a network processor 失效
    网络处理器的软件管理树实现

    公开(公告)号：US07107265B1

    公开(公告)日：2006-09-12

    申请号：US09545100

    申请日：2000-04-06

    申请人： Jean Louis Calvignac ,  Marco C. Heddes ,  Clark Debs Jeffries ,  Piyush Chunilal Patel ,  Mark Anthony Rinaldi

    发明人： Jean Louis Calvignac ,  Marco C. Heddes ,  Clark Debs Jeffries ,  Piyush Chunilal Patel ,  Mark Anthony Rinaldi

    IPC分类号： G06F17/30 ,  G06F15/00 ,  G06F9/44

    CPC分类号： H04L45/742 ,  G06F17/30961 ,  G06F17/30985 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99937

    摘要： Novel data structures, methods and apparatus for a Software Managed Tree (SMT) which provides a mechanism to create tree structures that follow a search mechanism defined by a control point processor. The search mechanism does not require storage on the previous pointer and uses only a forward pointer along with a next bit or group of bits to test thereby reducing storage space for nodes. The search mechanism processes multiple filter rules for an application without requiring multiple searches and also allows various filter rules to be chained. Two patterns of the same length are stored in each leaf to define a range compare. A compare at the end operation is either a compare under range or a compare under mask. In a compare under range, the input key is checked to determine if it is in the range defined by the two patterns. In a compare under mask, the bits in the input key are compared with the bits in a first leaf pattern under a mask specified in a second leaf pattern.

    摘要翻译： 用于软件管理树（SMT）的新型数据结构，方法和装置，其提供了一种机制，用于创建遵循由控制点处理器定义的搜索机制的树结构。 搜索机制不需要在前一个指针上存储，并且仅使用前向指针以及下一个位或一组位来进行测试，从而减少节点的存储空间。 搜索机制处理应用程序的多个过滤器规则，而不需要多次搜索，并且还允许链接各种过滤器规则。 在每个叶中存储相同长度的两个图案以定义范围比较。 在最终操作中的比较是在范围之下的比较或掩码下的比较。 在范围比较范围内，检查输入键以确定是否在两种模式定义的范围内。 在掩码下的比较中，将输入密钥中的比特与在第二叶图案中指定的掩码下的第一叶图案中的比特进行比较。

    System and method and computer program for filtering using tree structure
    38.
    发明授权
    System and method and computer program for filtering using tree structure 失效
    使用树结构进行过滤的系统和方法以及计算机程序

    公开(公告)号：US06298340B1

    公开(公告)日：2001-10-02

    申请号：US09312148

    申请日：1999-05-14

    申请人： Jean Louis Calvignac ,  Everett Arthur Corl, Jr. ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Clark Debs Jeffries ,  Piyush Chunilal Patel ,  Mark Anthony Rinaldi ,  Colin Beaton Verrilli

    发明人： Jean Louis Calvignac ,  Everett Arthur Corl, Jr. ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Clark Debs Jeffries ,  Piyush Chunilal Patel ,  Mark Anthony Rinaldi ,  Colin Beaton Verrilli

    IPC分类号： G06F1730

    CPC分类号： G06F17/30961 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99943 ,  Y10S707/99944

    摘要： A classification system includes a software managed tree testing bits from a key which labels an item. The bits are chosen by application of the Choice Bit Algorithm to the Rules in a Database of Rules. A controller including logic parses an unknown Key for bits to be tested in the decision nodes of a binary tree. Tests dictated by the tree are conducted in a predetermined way until all but one Rule from the database or all but a few Rules from the database are eliminated from consideration, whereupon the Key is fully tested by the one remaining Rule or in a lattice constructed of the remaining plurality of Rules, to determine an action to enforce on the item. Certain compare tests are used in the binary tree for the case that otherwise identical or similar rules are applied to integer ranges of key values which do not fall upon power of 2 boundaries. Furthermore, some very frequently occurring rules in such final tests might be designated as secondary rules, the remaining rules designated as primary rules, the entire decision tree recalculated using only primary rules, and the primary rules then connected to secondary rules only when logically necessary by means of a system of pointers making use of relative priorities of rules.

    摘要翻译： 分类系统包括从标签项目的键的软件管理树测试位。 通过将选择位算法应用于规则数据库中的规则来选择位。 包含逻辑的控制器在二叉树的决策节点中解析要测试的位的未知密钥。 由树进行的测试以预定的方式进行，直到从数据库中除了一个规则之外的所有除了数据库中的所有规则或从数据库中除了少数几个规则之外的所有测试都被消除，由此Key被完整的一个规则或由 剩余的多个规则，以确定对该项目执行的操作。 在二叉树中使用某些比较测试，否则相同或相似的规则应用于不落在2边界的幂的关键值的整数范围。 此外，这些最终测试中的一些非常频繁出现的规则可能被指定为次要规则，剩余的规则被指定为主要规则，仅使用主要规则重新计算的整个决策树，然后仅在逻辑上必要时连接到次级规则的主要规则 使用指针的相对优先级的指针系统的手段。

    Indicating data buffer by last bit flag
    40.
    发明授权
    Indicating data buffer by last bit flag 失效
    用最后一位标志指示数据缓冲区

    公开(公告)号：US07904617B2

    公开(公告)日：2011-03-08

    申请号：US12100739

    申请日：2008-04-10

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    IPC分类号： G06F5/00 ,  G06F15/16

    CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

    摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

    摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一”或“零”的单个位，并且指示何时发送具有最后位的数据缓冲器。 当附加数据缓冲器被链接到先前的数据缓冲器，指示要发送附加数据缓冲器时，最后一位处于第一位置，而当没有附加数据缓冲器被链接到先前数据缓冲器时，最后一位处于第一位置。 最后一位的位置被传送到指示特定帧的结束的网络处理器。