公开(公告)号：US07517766B2

公开(公告)日：2009-04-14

申请号：US11531260

申请日：2006-09-12

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

摘要翻译： 一种去除间隔物的方法，制造金属氧化物半导体晶体管器件的方法和金属氧化物半导体晶体管器件，其中在去除间隔物之前，保护层沉积在间隔物上 形成在源极/漏极区域上的材料层（例如自对准硅化物层）和栅电极，使得隔离物上的保护层的厚度小于材料层上的厚度，然后保护层部分 去除，使得隔离物上的保护层的厚度近似为零，并且保护层的一部分保留在材料层上。 因此，当去除间隔物时，材料层可被保护层保护。

公开(公告)号：US20080191287A1

公开(公告)日：2008-08-14

申请号：US11674660

申请日：2007-02-13

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

摘要翻译： 首先，提供具有第一有源区和第二有源区的半导体基板。 第一有源区包括第一晶体管，第二有源区包括第二晶体管。 第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。 通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。 去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

公开(公告)号：US20080150041A1

公开(公告)日：2008-06-26

申请号：US12042345

申请日：2008-03-05

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

公开(公告)号：US08828815B2

公开(公告)日：2014-09-09

申请号：US12959393

申请日：2010-12-03

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

摘要翻译： 首先，提供具有第一有源区和第二有源区的半导体基板。 第一有源区包括第一晶体管，第二有源区包括第二晶体管。 第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。 通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。 去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

公开(公告)号：US07868390B2

公开(公告)日：2011-01-11

申请号：US11674660

申请日：2007-02-13

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L29/76

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

摘要翻译： 首先，提供具有第一有源区和第二有源区的半导体基板。 第一有源区包括第一晶体管，第二有源区包括第二晶体管。 第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。 通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。 去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

公开(公告)号：US07615434B2

公开(公告)日：2009-11-10

申请号：US11389617

申请日：2006-03-24

申请人： Shih-Wei Sun ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Pei-Yu Chou

发明人： Shih-Wei Sun ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Pei-Yu Chou

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

摘要： A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation structure. Further, the first-type MOS transistor is disposed on the first active area of the substrate, and the second-type MOS transistor is disposed on the second active area of the substrate. The first stress layer is compliantly disposed on the first-type MOS transistor of the first active area. The first liner layer is compliantly disposed on the first stress layer. The second stress layer is compliantly disposed on the second-type MOS transistor of the second active area.

摘要翻译： 提供一种CMOS器件，包括衬底，第一类型MOS晶体管，第二类型MOS晶体管，第一应力层，第一衬里层和第二应力层。 衬底具有由隔离结构隔开的第一有源区和第二有源区。 此外，第一型MOS晶体管设置在衬底的第一有源区上，并且第二型MOS晶体管设置在衬底的第二有源区上。 第一应力层顺应地设置在第一有源区的第一型MOS晶体管上。 第一衬里层顺应地设置在第一应力层上。 第二应力层顺从地设置在第二有源区的第二型MOS晶体管上。

公开(公告)号：US08633549B2

公开(公告)日：2014-01-21

申请号：US13267068

申请日：2011-10-06

申请人： Chieh-Te Chen ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Yi-Po Lin

发明人： Chieh-Te Chen ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Yi-Po Lin

IPC分类号： H01L27/11 ,  H01L21/8234 ,  H01L21/8244

CPC分类号： H01L21/28079 ,  H01L21/027 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/8232 ,  H01L27/0629

摘要： A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.

摘要翻译： 半导体器件包括金属栅电极，无源器件和硬掩模层。 无源器件具有多晶硅元件层。 硬掩模层设置在金属栅电极和无源电极上，并且具有彼此基本共面的第一开口和第二开口，其中金属栅极电极和多晶硅元件层分别经由第一开口暴露， 第二个开口 并且第一开口和金属栅电极之间的距离基本上小于第二开口和多晶硅元件层之间的距离。

公开(公告)号：US20130087861A1

公开(公告)日：2013-04-11

申请号：US13267068

申请日：2011-10-06

申请人： Chieh-Te CHEN ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Yi-Po Lin

发明人： Chieh-Te CHEN ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Yi-Po Lin

IPC分类号： H01L27/10 ,  H01L21/8234

CPC分类号： H01L21/28079 ,  H01L21/027 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/8232 ,  H01L27/0629

摘要： A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.

摘要翻译： 半导体器件包括金属栅电极，无源器件和硬掩模层。 无源器件具有多晶硅元件层。 硬掩模层设置在金属栅电极和无源电极上，并且具有彼此基本共面的第一开口和第二开口，其中金属栅极电极和多晶硅元件层分别经由第一开口暴露， 第二个开口 并且第一开口和金属栅电极之间的距离基本上小于第二开口和多晶硅元件层之间的距离。

公开(公告)号：US08324038B2

公开(公告)日：2012-12-04

申请号：US12275181

申请日：2008-11-20

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

摘要翻译： 一种去除间隔物的方法，制造金属氧化物半导体晶体管器件的方法和金属氧化物半导体晶体管器件，其中在去除间隔物之前，保护层沉积在间隔物上 形成在源极/漏极区域上的材料层（例如自对准硅化物层）和栅电极，使得隔离物上的保护层的厚度小于材料层上的厚度，然后保护层部分 去除，使得隔离物上的保护层的厚度近似为零，并且保护层的一部分保留在材料层上。 因此，当去除间隔物时，材料层可被保护层保护。

公开(公告)号：US20090075441A1

公开(公告)日：2009-03-19

申请号：US12275181

申请日：2008-11-20

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/306 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.