Methods of forming fin field effect transistors using oxidation barrier layers
    32.
    发明授权
    Methods of forming fin field effect transistors using oxidation barrier layers 有权
    使用氧化阻挡层形成鳍状场效应晶体管的方法

    公开(公告)号:US07297600B2

    公开(公告)日:2007-11-20

    申请号:US11020899

    申请日:2004-12-23

    IPC分类号: H01L21/336

    摘要: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

    摘要翻译: 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。 在鳍状有源区的上表面和相对侧壁上形成氧化物层。 在翅片状有源区域的相对的侧壁上形成氧化阻挡层,并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。 翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层,并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。 氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化,大约在鳍状有源区的顶表面和基底之间的一半处。 还讨论了相关设备。

    Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures
    34.
    发明申请
    Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures 有权
    形成具有多沟道MOS晶体管和相关中间结构的半导体器件的方法

    公开(公告)号:US20050112851A1

    公开(公告)日:2005-05-26

    申请号:US10974410

    申请日:2004-10-27

    摘要: In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

    摘要翻译: 在制造半导体器件的方法中,在衬底上形成包括栅极层和沟道层的初步有源图案。 交替层叠栅极层和沟道层。 在初步活性图案上形成硬掩模。 使用硬掩模作为蚀刻掩模来部分蚀刻预活性图案以暴露基板的表面。 蚀刻的预活化图案被修整以形成宽度小于硬掩模的较低宽度的有源通道图案。 源极/漏极层形成在有源沟道图案和表面的暴露侧面上。 选择性地蚀刻栅极层以形成隧道。 门将包围活动通道模式并填充隧道。 还公开了相关的中间结构。

    Semiconductor device having floating body element and bulk body element
    36.
    发明授权
    Semiconductor device having floating body element and bulk body element 有权
    具有浮体元件和散装体元件的半导体器件

    公开(公告)号:US08178924B2

    公开(公告)日:2012-05-15

    申请号:US12146016

    申请日:2008-06-25

    IPC分类号: H01L27/12

    摘要: A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body element region and floating body element regions. An isolation region defining an active region of the bulk body element region of the substrate and defining first buried patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element regions of the substrate is provided. A first buried dielectric layer interposed between the first buried patterns and the substrate and between the first buried patterns and the first active patterns is provided.

    摘要翻译: 提供了具有浮体元件和本体元件的半导体器件及其制造方法。 半导体器件包括具有块体元件区域和浮体元件区域的衬底。 隔离区域限定衬底的本体元件区域的有源区域,并且限定顺序地堆叠在衬底的浮体元件区域的第一元件区域上的第一掩埋图案和第一有源图案。 设置介于第一掩埋图案和基板之间以及第一掩埋图案和第一有源图案之间的第一掩埋介质层。