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    Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures
    3.
    发明授权
    Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures 有权
    形成具有多沟道MOS晶体管和相关中间结构的半导体器件的方法

    公开(公告)号：US07800172B2

    公开(公告)日：2010-09-21

    申请号：US11941656

    申请日：2007-11-16

    申请人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

    发明人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66484 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696

    摘要： In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

    摘要翻译： 在制造半导体器件的方法中，在衬底上形成包括栅极层和沟道层的初步有源图案。 交替层叠栅极层和沟道层。 在初步活性图案上形成硬掩模。 使用硬掩模作为蚀刻掩模来部分蚀刻预活性图案以暴露基板的表面。 蚀刻的预活化图案被修整以形成宽度小于硬掩模的较低宽度的有源通道图案。 源极/漏极层形成在有源沟道图案和表面的暴露侧面上。 选择性地蚀刻栅极层以形成隧道。 一个门包围有源通道模式并填充隧道。 还公开了相关的中间结构。

    Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures
    4.
    发明申请
    Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures 有权
    形成具有多沟道MOS晶体管和相关中间结构的半导体器件的方法

    公开(公告)号：US20050112851A1

    公开(公告)日：2005-05-26

    申请号：US10974410

    申请日：2004-10-27

    申请人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

    发明人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/66484 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696

    摘要： In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

    摘要翻译： 在制造半导体器件的方法中，在衬底上形成包括栅极层和沟道层的初步有源图案。 交替层叠栅极层和沟道层。 在初步活性图案上形成硬掩模。 使用硬掩模作为蚀刻掩模来部分蚀刻预活性图案以暴露基板的表面。 蚀刻的预活化图案被修整以形成宽度小于硬掩模的较低宽度的有源通道图案。 源极/漏极层形成在有源沟道图案和表面的暴露侧面上。 选择性地蚀刻栅极层以形成隧道。 门将包围活动通道模式并填充隧道。 还公开了相关的中间结构。

    Methods of Forming Semiconductor Devices Having Multiple Channel MOS Transistors and Related Intermediate Structures
    5.
    发明申请
    Methods of Forming Semiconductor Devices Having Multiple Channel MOS Transistors and Related Intermediate Structures 有权
    形成具有多通道MOS晶体管和相关中间结构的半导体器件的方法

    公开(公告)号：US20080093628A1

    公开(公告)日：2008-04-24

    申请号：US11941656

    申请日：2007-11-16

    申请人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

    发明人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

    IPC分类号： H01L29/778

    CPC分类号： H01L29/66484 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696

    摘要： In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

    摘要翻译： 在制造半导体器件的方法中，在衬底上形成包括栅极层和沟道层的初步有源图案。 交替层叠栅极层和沟道层。 在初步活性图案上形成硬掩模。 使用硬掩模作为蚀刻掩模来部分蚀刻预活性图案以暴露基板的表面。 蚀刻的预活化图案被修整以形成宽度小于硬掩模的较低宽度的有源通道图案。 源极/漏极层形成在有源沟道图案和表面的暴露侧面上。 选择性地蚀刻栅极层以形成隧道。 一个门包围有源通道模式并填充隧道。 还公开了相关的中间结构。

    Methods of forming semiconductor devices having multiple channel MOS transistors
    6.
    发明授权
    Methods of forming semiconductor devices having multiple channel MOS transistors 有权
    形成具有多通道MOS晶体管的半导体器件的方法

    公开(公告)号：US07316968B2

    公开(公告)日：2008-01-08

    申请号：US10974410

    申请日：2004-10-27

    申请人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

    发明人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

    IPC分类号： H01L21/00

    CPC分类号： H01L29/66484 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696

    摘要： In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

    摘要翻译： 在制造半导体器件的方法中，在衬底上形成包括栅极层和沟道层的初步有源图案。 交替层叠栅极层和沟道层。 在初步活性图案上形成硬掩模。 使用硬掩模作为蚀刻掩模来部分蚀刻预活性图案以暴露基板的表面。 蚀刻的预活化图案被修整以形成宽度小于硬掩模的较低宽度的有源通道图案。 源极/漏极层形成在有源沟道图案和表面的暴露侧面上。 选择性地蚀刻栅极层以形成隧道。 门将包围活动通道模式并填充隧道。 还公开了相关的中间结构。

    Method of fabricating a multi-bit electro-mechanical memory device
    8.
    发明授权
    Method of fabricating a multi-bit electro-mechanical memory device 有权
    制造多位机电存储器件的方法

    公开(公告)号：US07790494B2

    公开(公告)日：2010-09-07

    申请号：US12007819

    申请日：2008-01-16

    申请人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

    发明人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

    IPC分类号： H01L21/00 ,  H01L35/24 ,  H01L51/00 ,  H01L29/792

    CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  H01L29/0665 ,  H01L29/0673

    摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

    摘要翻译： 存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。 位线可以在第一方向上形成在基板上。 第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。 焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。 第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。 第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

    Metal oxide semiconductor (MOS) transistors having three dimensional channels
    9.
    发明授权
    Metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
    具有三维通道的金属氧化物半导体（MOS）晶体管

    公开(公告)号：US07473963B2

    公开(公告)日：2009-01-06

    申请号：US11854734

    申请日：2007-09-13

    申请人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    发明人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7842

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。 第一和第二沟道区设置在源区和漏区之间。 沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。 第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。 在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

    Memory device and method of fabricating the same
    10.
    发明申请
    Memory device and method of fabricating the same 有权
    存储器件及其制造方法

    公开(公告)号：US20080185668A1

    公开(公告)日：2008-08-07

    申请号：US12007819

    申请日：2008-01-16

    申请人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

    发明人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

    IPC分类号： H01L29/84 ,  H01L21/00

    CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  H01L29/0665 ,  H01L29/0673

    摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

    摘要翻译： 存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。 位线可以在第一方向上形成在基板上。 第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。 焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。 第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。 第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。