公开(公告)号：US06201303B1

公开(公告)日：2001-03-13

申请号：US09417842

申请日：1999-10-14

申请人： Minh Van Ngo ,  Paul R. Besser ,  Yowjuang Bill Liu

发明人： Minh Van Ngo ,  Paul R. Besser ,  Yowjuang Bill Liu

IPC分类号： H01L2348

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge introduces additional nitrogen by ion implantation into a nitrogen-containing etch stop layer (e.g., SiON) that has already been deposited, by plasma enhanced chemical vapor deposition (PECVD), for example. The enriched nitrogen etch stop layer is harder to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.

摘要翻译： 用于形成局部互连而不削弱场边缘或在场边缘断开扩散区域的方法和装置通过离子注入将额外的氮引入通过等离子体已经沉积的含氮蚀刻停止层（例如，SiON） 增强化学气相沉积（PECVD）。 富集的氮蚀刻停止层比常规PECVD SiON难以蚀刻，使得当蚀刻其中随后沉积局部互连材料的介电层时，蚀刻以受控的方式停止在蚀刻停止层处。 这防止了在场边缘处的硅化物区域和扩散区域的无意蚀刻。

公开(公告)号：US06171947B2

公开(公告)日：2001-01-09

申请号：US09209367

申请日：1998-12-08

申请人： Suzette K. Pangrle ,  Paul R. Besser ,  Minh Van Ngo ,  Stephan Keetai Park ,  Susan Tovar

发明人： Suzette K. Pangrle ,  Paul R. Besser ,  Minh Van Ngo ,  Stephan Keetai Park ,  Susan Tovar

IPC分类号： H01L2131

CPC分类号： H01L21/3145 ,  H01L21/76834

摘要： In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, the substrate and interconnect lines are annealed prior to deposition of an ILD. A post annealing SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. Additionally, during deposition, minor adjustments are made to deposition temperature and process pressure to control the optical characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing. The pre-ILD annealing results in a substantially reduced incidence of stress-induced voiding in the underlying interconnect lines. Furthermore, the pre-ILD annealing can be combined with other advantageous process environments to more significantly reduce the incidence of stress-induced voiding in the underlying interconnect lines. Such combinations include process temperature reduction to below about 380 degrees Celsius and reduction of silane flow rate to less than about sixty standard cubic centimeters per minute.

摘要翻译： 在用于在衬底的微电路互连线上形成层间电介质（ILD）涂层的方法中，衬底和互连线在沉积ILD之前被退火。 通过使用等离子体增强化学气相沉积形成后退火SiON层。 使用由氮气，一氧化二氮和硅烷气体形成的等离子体的沉积，其中气体以稳定的流速分配并由射频电源激励。 等离子体反应形成沉积在半导体衬底上的SiON。 此外，在沉积期间，对沉积温度和工艺压力进行微调，以控制SiON层的光学特性。 测试SiON层的可接受的光学性能，并且用SiO 2层涂覆可接受的SiON层以完成ILD的形成。 一旦形成了ILD，底物就可以进行进一步的处理。 前ILD退火导致底层互连线中应力诱发的排泄的发生率显着降低。 此外，前ILD退火可以与其他有利的工艺环境组合，以更显着地降低底层互连线中的应力诱发的排空的发生。 这样的组合包括将工艺温度降低至低于约380摄氏度，并将硅烷流速降低至小于约60标准立方厘米每分钟。

公开(公告)号：US06566252B1

公开(公告)日：2003-05-20

申请号：US09689144

申请日：2000-10-11

申请人： Paul R. Besser ,  Minh Van Ngo

发明人： Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L2144

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76801

摘要： A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.

摘要翻译： 制造0.25微米半导体芯片的方法包括使用TEOS作为高密度等离子体（HDP）层间电介质（ILD）。 更具体地说，在基板上建立预定的铝线图案之后，TEOS沉积并与TEOS沉积同时被蚀刻掉，从而避免了铝线中的氢脆化和随后的空隙形成，否则如果硅烷是 用作HDP ILD。

公开(公告)号：US06534869B2

公开(公告)日：2003-03-18

申请号：US09128057

申请日：1998-07-29

申请人： Bryan Tracy ,  Paul R. Besser ,  Minh Van Ngo

发明人： Bryan Tracy ,  Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L2352

CPC分类号： H01L21/76858 ,  H01L21/76841 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms first, which subsequently volumetrically contracts, thereby forming a titanium aluminide compound, with the contraction being absorbed by the aluminum. Because the alloy is reacted to form the metal compound prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.

摘要翻译： 制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火过程中，首先形成铝和钛的合金，其随后体积收缩，由此形成铝化铝化合物，其中收缩被铝吸收。 因为在ILD沉积之前合金反应形成金属化合物，所以当它尝试吸收合金的收缩时，铝不受ILD的约束。 因此，互连线中不希望的空隙形成的可能性降低。

公开(公告)号：US06225216B1

公开(公告)日：2001-05-01

申请号：US09418490

申请日：1999-10-15

申请人： Minh Van Ngo ,  Yowjuang Bill Liu ,  Paul R. Besser

发明人： Minh Van Ngo ,  Yowjuang Bill Liu ,  Paul R. Besser

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/3185 ,  H01L21/76895

摘要： A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge provides an etch stop layer with increased density in comparison to conventionally deposited (e.g., plasma enhanced chemical vapor deposition (PECVD) etch stop layers. A low pressure chemical vapor deposition (LPCVD) process is used to deposit LPCVD SiN, using a high temperature in the deposition chamber. The increased temperature during deposition creates a highly dense, thermal SiN etch stop layer that is slower to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.

摘要翻译： 与常规沉积（例如，等离子体增强化学气相沉积（PECVD）蚀刻停止层（例如，等离子体增强化学气相沉积（PECVD））蚀刻停止层相比，用于形成局部互连而不削弱场边缘或在场边缘处断开扩散区域的方法和装置提供了具有增加的密度 使用低压化学气相沉积（LPCVD）工艺来沉积LPCVD SiN，使用沉积室中的高温，沉积过程中增加的温度产生高度致密的热SiN蚀刻停止层，其比常规PECVD蚀刻更慢 SiON，使得当蚀刻其中随后沉积局部互连材料的电介质层时，蚀刻以受控的方式停止在蚀刻停止层处，这防止了在场边缘处的硅化物区域和扩散区域的无意蚀刻。

公开(公告)号：US07713834B2

公开(公告)日：2010-05-11

申请号：US12205361

申请日：2008-09-05

申请人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US07670915B1

公开(公告)日：2010-03-02

申请号：US10791096

申请日：2004-03-01

申请人： Errol Todd Ryan ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Robert J. Chiu ,  Mehrdad Mahanpour ,  Minh Van Ngo

发明人： Errol Todd Ryan ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Robert J. Chiu ,  Mehrdad Mahanpour ,  Minh Van Ngo

IPC分类号： H01L21/20

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/7833

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结和栅极上形成硅化物。 在半导体衬底的上方形成有具有接触孔的层间电介质。 接触衬垫形成在接触孔中，然后在接触衬垫上形成接触。 接触衬垫是接触材料的氮化物，并且在低于硅化物的热预算的温度下形成。

公开(公告)号：US07648886B2

公开(公告)日：2010-01-19

申请号：US10341863

申请日：2003-01-14

申请人： Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫形成为能够减少锗除气的低温过程。 低温过程可以是UVO，ALD，CVD，PECVD或HDP工艺。

公开(公告)号：US06329718B1

公开(公告)日：2001-12-11

申请号：US09105775

申请日：1998-06-26

申请人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick MacCrae ,  Richard J. Huang ,  Khanh Tran

发明人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick MacCrae ,  Richard J. Huang ,  Khanh Tran

IPC分类号： H01L2348

CPC分类号： H01L21/7685 ,  H01L21/76837 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

摘要翻译： 用于制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火期间，形成铝和钛的合金，其随后容积收缩，收缩被铝吸收。 因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。 因此，互连线中不希望的空隙形成的可能性降低。 在随后的ILD间隙填充沉积过程中，通过使用相对低的偏置功率来降低气相沉积温度，并且通过使用相对较低的源气体沉积流速来减少互连线上的流动引起的压缩应力，仍然进一步降低了不希望的空隙形成的可能性 在ILD形成期间。

公开(公告)号：US06228761B1

公开(公告)日：2001-05-08

申请号：US09417840

申请日：1999-10-14

申请人： Minh Van Ngo ,  Paul R. Besser

发明人： Minh Van Ngo ,  Paul R. Besser

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L21/76895

摘要： A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge introduces additional nitrogen from a nitrogen plasma into a nitrogen-containing etch stop layer (e.g., SiON) that has already been deposited by plasma enhanced chemical vapor deposition (PECVD), for example. The enriched nitrogen etch stop layer is harder to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is to be subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.

摘要翻译： 用于形成局部互连而不削弱场边缘或在场边缘处断开扩散区的方法和装置将来自氮等离子体的附加氮引入已经通过等离子体沉积的含氮蚀刻停止层（例如，SiON） 增强化学气相沉积（PECVD）。 富集的氮蚀刻停止层比常规PECVD SiON难以蚀刻，使得当蚀刻其中将要沉积局部互连材料的电介质层时，蚀刻以受控的方式在蚀刻停止层处停止。 这防止了在场边缘处的硅化物区域和扩散区域的无意蚀刻。