公开(公告)号：US07200696B2

公开(公告)日：2007-04-03

申请号：US09828342

申请日：2001-04-06

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F15/16

CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit feature is communicated to the network processor to indicate whether the transmission of a particular frame is ended and a new frame is to be transmitted.

摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括多个控制块，一个用于每个数据缓冲器，每个控制块包含用于将一个缓冲器链接到另一缓冲器以进行传输的控制信息。 每个控制块具有作为单个位的最后位特征，并且指示何时发送具有最后位的数据缓冲器。 这最后一位功能是一个可以设置为零或一个的位。 当附加数据缓冲器被链接到先前的数据缓冲器指示要发送附加数据缓冲器时，最后一位特征处于第一位置，而当没有附加数据缓冲器被链接到先前的数据缓冲器时，第二位置 。 将最后一位特征的位置传送给网络处理器，以指示特定帧的传输是否结束，并且要发送新的帧。

公开(公告)号：US07921396B2

公开(公告)日：2011-04-05

申请号：US12126951

申请日：2008-05-26

申请人： Fabrice Jean Verplanken ,  Jean-Paul Aldebert ,  Claude Basso ,  Jean Louis Calvignac

发明人： Fabrice Jean Verplanken ,  Jean-Paul Aldebert ,  Claude Basso ,  Jean Louis Calvignac

IPC分类号： G06F17/50

CPC分类号： H04L69/16 ,  H04L49/45 ,  H04L69/161

摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

公开(公告)号：US20080222324A1

公开(公告)日：2008-09-11

申请号：US12120419

申请日：2008-05-14

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F5/00

CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

公开(公告)号：US06937606B2

公开(公告)日：2005-08-30

申请号：US09839010

申请日：2001-04-20

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： H04L12/56 ,  H04L29/06

CPC分类号： H04L69/16 ,  H04L29/06 ,  H04L49/90 ,  H04L49/9094 ,  H04L69/161 ,  H04L69/166 ,  H04L69/22

摘要： Data structures, a method, and an associated transmission system for IP fragmentation and IP reassembly on network processors in order to minimize memory allocation requirements. Frame data for IP fragmentation or reassembly on a network processor is read into buffers to which are associated various control structures. The control structures permit IP fragmentation or reassembly to be accomplished without creating multiple copies of the frame or fragments.

摘要翻译： 数据结构，方法和相关的传输系统，用于网络处理器上的IP分段和IP重组，以最大限度地减少内存分配要求。 在网络处理器上进行IP分片或重组的帧数据被读入到与各种控制结构相关联的缓冲器中。 控制结构允许在不产生帧或片段的多个副本的情况下实现IP分片或重组。

公开(公告)号：US20080229272A1

公开(公告)日：2008-09-18

申请号：US12126953

申请日：2008-05-26

申请人： Fabrice Jean Verplanken ,  Jean-Paul Aldebert ,  Claude Basso ,  Jean Louis Calvignac

发明人： Fabrice Jean Verplanken ,  Jean-Paul Aldebert ,  Claude Basso ,  Jean Louis Calvignac

IPC分类号： G06F17/50 ,  G06F15/16

CPC分类号： H04L69/16 ,  H04L49/45 ,  H04L69/161

摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

公开(公告)号：US20080215772A1

公开(公告)日：2008-09-04

申请号：US12100739

申请日：2008-04-10

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F5/00

CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一”或“零”的单个位，并且指示何时发送具有最后位的数据缓冲器。 当附加数据缓冲器被链接到先前的数据缓冲器，指示要发送附加数据缓冲器时，最后一位处于第一位置，而当没有附加数据缓冲器被链接到先前数据缓冲器时，最后一位处于第一位置。 最后一位的位置被传送到指示特定帧的结束的网络处理器。

公开(公告)号：US20110158250A1

公开(公告)日：2011-06-30

申请号：US12650120

申请日：2009-12-30

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

IPC分类号： H04L12/56

CPC分类号： H04L49/9047

摘要： A method and apparatus for assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. In a given processing period, sinks that are available to receive work are identified and sources qualified to send work to the available sinks are determined taking into account any assignment constraints. A single source is selected from an overlap of the qualified sources and sources having work available. This selection may be made using a hierarchical source scheduler for processing subsets of supported sources simultaneously in parallel. A sink to which work from the selected source may be assigned is selected from available sinks qualified to receive work from the selected source.

摘要翻译： 一种用于从多个源（例如网络处理设备中的数据队列）将诸如数据分组的工作分配给诸如网络处理设备中的处理器线程的多个接收器的方法和装置。 在给定的处理期间，确定可用于接收工作的接收器，并且考虑到任何分配约束来确定用于将工作发送到可用接收器的资源。 从具有可用工作的合格来源和源的重叠中选择单个来源。 可以使用用于并行同时处理所支持的源的子集的分级源调度器来进行该选择。 从可选择的来源可以分配工作的接收端从有资格从所选源接收工作的可用接收器中选择。

公开(公告)号：US08532129B2

公开(公告)日：2013-09-10

申请号：US12650120

申请日：2009-12-30

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

IPC分类号： H04L12/28

CPC分类号： H04L49/9047

摘要： Assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device is provided. In a given processing period, sinks that are available to receive work are identified and sources qualified to send work to the available sinks are determined taking into account any assignment constraints. A single source is selected from an overlap of the qualified sources and sources having work available. This selection may be made using a hierarchical source scheduler for processing subsets of supported sources simultaneously in parallel. A sink to which work from the selected source may be assigned is selected from available sinks qualified to receive work from the selected source.

摘要翻译： 提供了诸如数据分组的工作，诸如诸如网络处理设备中的数据队列的多个源到网络处理设备中的诸如处理器线程的多个接收器。 在给定的处理期间，确定可用于接收工作的接收器，并且考虑到任何分配约束来确定用于将工作发送到可用接收器的资源。 从具有可用工作的合格来源和源的重叠中选择单个来源。 可以使用用于并行同时处理所支持的源的子集的分级源调度器来进行该选择。 从可选择的来源可以分配工作的接收端从有资格从所选源接收工作的可用接收器中选择。

公开(公告)号：US09215125B2

公开(公告)日：2015-12-15

申请号：US13884664

申请日：2011-12-19

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Damon Philippe ,  Natarajan Vaidhyanathan ,  Colin B. Verrilli ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Damon Philippe ,  Natarajan Vaidhyanathan ,  Colin B. Verrilli ,  Fabrice Jean Verplanken

IPC分类号： H04L29/06 ,  G06F9/38 ,  G06F15/163 ,  G06F9/54

CPC分类号： H04L29/0653 ,  G06F9/3877 ,  G06F9/544 ,  G06F13/385 ,  G06F15/163 ,  H04L69/22

摘要： A network processor includes first communication protocol ports that each support ‘M’ minimum size packet data path traffic on ‘N’ lanes at ‘S’ Gigabits per second (Gbps) and traffic with different communication protocol units on ‘n’ additional lanes at ‘s’ Gbps. The first communication protocol ports support access to an external coprocessor using parsing logic located in each of the first communication protocol ports. The parsing logic, during a parsing period, is configured to send a request to the external coprocessor at reception of a ‘M’ size packet and to receive a response from the external coprocessor. The parsing logic sends a request maximum ‘m’ size byte word to the external coprocessor on one of the additional lanes and receives a response maximum ‘m’ size byte word from the external coprocessor on the one of the additional lanes while complying with the equation N×S/M=

摘要翻译： 网络处理器包括第一通信协议端口，每个端口以“S”千兆位/秒（Gbps）在“N”通道上支持“M”个最小尺寸分组数据路径业务，并且在“n”个附加车道上以不同的通信协议单元的流量“ s Gbps 第一通信协议端口支持使用位于每个第一通信协议端口中的解析逻辑来访问外部协处理器。 解析逻辑在解析周期期间被配置为在接收到“M”大小的分组时向外部协处理器发送请求并且从外部协处理器接收响应。 解析逻辑在附加通道之一上向外部协处理器发送请求最大“m”字节字，并在附加通道之一上从外部协处理器接收响应最大“m”字节字，同时遵循等式 N×S / M =

公开(公告)号：US20130308653A1

公开(公告)日：2013-11-21

申请号：US13884664

申请日：2011-12-19

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Damon Philippe ,  Natarajan Vaidhyanathan ,  Colin B. Verrilli ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Damon Philippe ,  Natarajan Vaidhyanathan ,  Colin B. Verrilli ,  Fabrice Jean Verplanken

IPC分类号： H04L29/06

CPC分类号： H04L29/0653 ,  G06F9/3877 ,  G06F9/544 ,  G06F13/385 ,  G06F15/163 ,  H04L69/22

摘要： A network processor includes first communication protocol ports that each support ‘M’ minimum size packet data path traffic on ‘N’ lanes at ‘S’ Gigabits per second (Gbps) and traffic with different communication protocol units on ‘n’ additional lanes at ‘s’ Gbps. The first communication protocol ports support access to an external coprocessor using parsing logic located in each of the first communication protocol ports. The parsing logic, during a parsing period, is configured to send a request to the external coprocessor at reception of a ‘M’ size packet and to receive a response from the external coprocessor. The parsing logic sends a request maximum ‘m’ size byte word to the external coprocessor on one of the additional lanes and receives a response maximum ‘m’ size byte word from the external coprocessor on the one of the additional lanes while complying with the equation N×S/M=

摘要翻译： 网络处理器包括第一通信协议端口，每个端口以“S”千兆位/秒（Gbps）在“N”通道上支持“M”个最小尺寸分组数据路径业务，并且在“n”个附加车道上以不同的通信协议单元的流量“ s Gbps 第一通信协议端口支持使用位于每个第一通信协议端口中的解析逻辑来访问外部协处理器。 解析逻辑在解析周期期间被配置为在接收到“M”大小的分组时向外部协处理器发送请求并且从外部协处理器接收响应。 解析逻辑在附加通道之一上向外部协处理器发送请求最大“m”字节字，并在附加通道之一上从外部协处理器接收响应最大“m”字节字，同时遵循等式 N×S / M =