Method for determining BSIMSOI4 DC model parameters
    31.
    发明授权
    Method for determining BSIMSOI4 DC model parameters 有权
    确定BSIMSOI4 DC模型参数的方法

    公开(公告)号:US09134361B2

    公开(公告)日:2015-09-15

    申请号:US13696455

    申请日:2011-09-25

    IPC分类号: G06F7/60 G01R31/26 G06F17/50

    摘要: The present invention provides a method for determining BSIMSOI4 Direct Current (DC) model parameters, where a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices of a body leading-out structure and of different sizes, and a plurality of MOSFET devices of a floating structure and of different sizes are provided; Id-Vg-Vp, Id/Ip-Vd-Vg, Ig-Vg-Vd, Ig-Vp, Ip-Vg-vd, Is/Id-Vp, and Id/Ip-Vp-Vd properties of all the MOSFET devices of a body leading-out structure, and Id-Vg-Vp, Id-Vd-Vg, and Ig-Vg-Vd properties of all the MOSFET devices of a floating structure are measured; electrical property curves without a self-heating effect of each MOSFET device of a body leading-out structure and each MOSFET device of a floating structure are obtained; and then DC parameters of a BSIMSOI4 model are successively extracted according to specific steps. In the present invention, proper test curves are successively selected according to model equations, and various kinds of parameters are successively determined, thereby accurately and effectively extracting the DC parameters of the BSIMSOI4 model.

    摘要翻译: 本发明提供了一种用于确定BSIMSOI4直流(DC)模型参数的方法,其中,体内引出结构和不同尺寸的多个金属氧化物半导体场效应晶体管(MOSFET)器件和多个MOSFET器件 提供浮动结构和不同尺寸; 所有MOSFET器件的Id-Vg-Vp,Id / Ip-Vd-Vg,Ig-Vg-Vd,Ig-Vp,Ip-Vg-vd,Is / Id-Vp和Id / Ip-Vp-Vd特性 测量浮体结构的所有MOSFET器件的体导体结构和Id-Vg-Vp,Id-Vd-Vg和Ig-Vg-Vd特性; 获得不具有体引出结构的每个MOSFET器件和浮置结构的每个MOSFET器件的自发热效应的电性能曲线; 然后根据具体步骤依次提取BSIMSOI4模型的DC参数。 在本发明中,根据模型方程依次选择适当的试验曲线,并连续确定各种参数,从而准确有效地提取BSIMSOI4型号的直流参数。

    PD SOI device with a body contact structure
    32.
    发明授权
    PD SOI device with a body contact structure 有权
    PD SOI器件具有体接触结构

    公开(公告)号:US08937354B2

    公开(公告)日:2015-01-20

    申请号:US13128907

    申请日:2010-09-08

    摘要: The present invention discloses a PD SOI device with a body contact structure. The active region of the PD SOI device includes: a body region; a gate region, which is inverted-L shaped, formed on the body region; a N-type source region and a N-type drain region, formed respectively at the two opposite sides of the anterior part the body region; a body contact region, formed at one side of the posterior part of the body region, which is side-by-side with the N-type source region; and a first silicide layer, formed on the body contact region and the N-type source region, which is contact to both of the body contact region and the N-type source region. The body contact region of the device is formed on the border of the source region and the leading-out terminal of the gate electrode. It can suppress floating body effect of the PD SOI device meanwhile not increasing the chip area, thereby overcoming the shortcoming in the prior art that the chip area is enlarged when the traditional body contact structure is employed. Furthermore, the fabrication process provided herein is simple and compatible to the CMOS technology.

    摘要翻译: 本发明公开了一种具有体接触结构的PD SOI器件。 PD SOI器件的有源区包括:主体区域; 形成在身体区域上的倒L形的栅极区域; 分别形成在身体区域的前部的两个相对侧的N型源极区域和N型漏极区域; 身体接触区域,形成在与N型源区并排的身体区域的后部的一侧; 以及形成在与所述本体接触区域和所述N型源极区域接触的所述本体接触区域和所述N型源极区域上的第一硅化物层。 器件的体接触区域形成在栅极电极的源极区域和引出端子的边界上。 它可以抑制PD SOI器件的浮体效应,同时不增加芯片面积,从而克服了现有技术中使用传统的体接触结构时芯片面积扩大的缺点。 此外,本文提供的制造工艺简单且与CMOS技术兼容。

    Method, network element, and mobile station for negotiating encryption algorithms
    33.
    发明授权
    Method, network element, and mobile station for negotiating encryption algorithms 有权
    方法,网元和移动台协商加密算法

    公开(公告)号:US08908863B2

    公开(公告)日:2014-12-09

    申请号:US13415681

    申请日:2012-03-08

    IPC分类号: H04L9/00 H04L29/06 H04W12/02

    摘要: A method, network element, and mobile station (MS) are disclosed. The method includes: obtaining information that a plug-in card of the MS does not support a first encryption algorithm; deleting the first encryption algorithm from an encryption algorithm list permitted by a core network element according to the information that the plug-in card of the MS does not support the first encryption algorithm; sending the encryption algorithm list excluding the first encryption algorithm to an access network element, so that the access network element selects an encryption algorithm according to the encryption algorithm list excluding the first encryption algorithm and the MS capability information sent from the MS and sends the selected encryption algorithm to the MS. By using the method, network element, and MS, errors due to the fact that the plug-in card of the MS does not support an encryption algorithm may be avoided during the encryption process.

    摘要翻译: 公开了一种方法,网元和移动台(MS)。 该方法包括:获取MS的插件卡不支持第一加密算法的信息; 根据MS的插件卡不支持第一加密算法的信息,从核心网元允许的加密算法列表中删除第一加密算法; 将不包括第一加密算法的加密算法列表发送到接入网元,使得接入网元根据除了第一加密算法之外的加密算法列表和从MS发送的MS能力信息选择加密算法,并发送所选择的 加密算法到MS。 通过使用该方法,网元和MS,由于MS的插件卡不支持加密算法的事实可能在加密过程期间被避免。

    Method and apparatus for security algorithm selection processing, network entity, and communication system
    34.
    发明授权
    Method and apparatus for security algorithm selection processing, network entity, and communication system 有权
    安全算法选择处理方法和装置,网络实体和通信系统

    公开(公告)号:US08898729B2

    公开(公告)日:2014-11-25

    申请号:US13251595

    申请日:2011-10-03

    IPC分类号: H04L29/06 H04W12/00

    摘要: Embodiments of the present invention disclose a method and an apparatus for security algorithm selection processing, a network entity, and a communication system. The method includes: receiving a service request message sent by user equipment; and according to a security protection requirement of the service request message, selecting a security algorithm from a security algorithm list supported by both the user equipment and a network entity, where security algorithm lists supported by the user equipment and/or the network entity are set separately based on different security protection requirements, or security algorithm lists supported by the user equipment and the network entity are used for indicating security capability of the user equipment and the network entity respectively.

    摘要翻译: 本发明的实施例公开了一种用于安全算法选择处理,网络实体和通信系统的方法和装置。 该方法包括:接收用户设备发送的业务请求消息; 并且根据所述服务请求消息的安全保护要求,从由用户设备和网络实体支持的安全算法列表中选择安全算法,其中设置由用户设备和/或网络实体支持的安全算法列表 分别基于不同的安全保护要求,或者由用户设备和网络实体支持的安全算法列表分别用于指示用户设备和网络实体的安全能力。

    MOS device for eliminating floating body effects and self-heating effects
    36.
    发明授权
    MOS device for eliminating floating body effects and self-heating effects 有权
    用于消除浮体效应和自发热效应的MOS器件

    公开(公告)号:US08710549B2

    公开(公告)日:2014-04-29

    申请号:US13128439

    申请日:2010-09-07

    IPC分类号: H01L29/66

    摘要: A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

    摘要翻译: 公开了一种用于消除浮体效应和自发热效应的SOI MOS器件。 该器件包括将有源栅极沟道耦合到Si衬底的连接层。 连接层在设备操作期间提供电气和热通道,可以消除浮体效应和自热效应。 详细公开了在Si活性通道和Si衬底之间具有SiGe连接器的MOS器件的实例,并提供制造工艺。

    TCAD emulation calibration method of SOI field effect transistor
    37.
    发明授权
    TCAD emulation calibration method of SOI field effect transistor 失效
    SOI场效应晶体管的TCAD仿真校准方法

    公开(公告)号:US08667440B2

    公开(公告)日:2014-03-04

    申请号:US13696401

    申请日:2011-09-23

    IPC分类号: G06F9/455 G06F17/50

    摘要: A calibration method for a device using TCAD to emulation SOI field effect transistor, where process emulation MOS device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; the process emulation MOS device structures are calibrated according to a TEM test result, a SIMS test result, a CV test result, a WAT test result, and a square resistance test result of an actual device, so as to complete TCAD emulation calibration of key electrical parameters of an SOI field effect transistor. Thereby, providing effective guidance for research, development and optimization of a new process flow are realized.

    摘要翻译: 一种使用TCAD仿真SOI场效应晶体管的器件的校准方法,其中通过建立TCAD过程仿真程序获得具有不同通道长度Lgate的工艺仿真MOS器件结构; 根据TEM测试结果,SIMS测试结果,CV测试结果,WAT测试结果和实际设备的方形电阻测试结果对过程仿真MOS器件结构进行校准,从而完成关键的TCAD仿真校准 SOI场效应晶体管的电参数。 从而实现了对新工艺流程的研究,开发和优化的有效指导。

    Vertical SOI bipolar junction transistor and manufacturing method thereof
    38.
    发明授权
    Vertical SOI bipolar junction transistor and manufacturing method thereof 失效
    垂直SOI双极结型晶体管及其制造方法

    公开(公告)号:US08629029B2

    公开(公告)日:2014-01-14

    申请号:US13055577

    申请日:2010-07-14

    IPC分类号: H01L21/331

    CPC分类号: H01L29/7317 H01L29/66265

    摘要: The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost.

    摘要翻译: 本发明公开了一种垂直SOI双极结型晶体管及其制造方法。 双极结型晶体管包括从下到上的包括主体区域,掩埋氧化物层和顶部硅膜的SOI衬底; 位于由STI工艺形成的顶部硅膜中的有源区; 位于靠近由离子注入形成的掩埋氧化物层的有源区域的集电极区域; 位于靠近通过离子注入形成的顶部硅膜的深度的有源区域中的基极区域; 发射极和基极两者都位于基极区域之上; 位于发射极和基极周围的侧壁间隔物。 利用简单的双重多晶硅技术的本发明不仅可以改善晶体管的性能,而且可以减小有源区的面积,以增加集成密度。 此外,本发明利用侧壁间隔物工艺来改善SOI BJT和SOI CMOS的相容性,这简化了SOI BiCMOS工艺,从而降低了成本。

    Method, apparatus, and system for preventing abuse of authentication vector
    39.
    发明授权
    Method, apparatus, and system for preventing abuse of authentication vector 有权
    用于防止认证向量滥用的方法,装置和系统

    公开(公告)号:US08600054B2

    公开(公告)日:2013-12-03

    申请号:US12892757

    申请日:2010-09-28

    IPC分类号: H04L9/32

    CPC分类号: H04W12/04 H04W12/10 H04W12/12

    摘要: A method for preventing abuse of an Authentication Vector (AV) and a system and apparatus for implementing the method are provided. Access network information of a non-3rd Generation Partnership Project (3GPP) access network where a user resides is bound to an AV of the user, so that when the user accesses an Evolved Packet System (EPS) through the non-3GPP access network, even if an entity in the non-3GPP access network is breached, or an Evolved Packet Data Gateway (ePDG) connected to an untrusted non-3GPP access network is breached, the stolen AV cannot be applied to other non-3GPP access networks by an attacker.

    摘要翻译: 提供了防止认证向量(AV)的滥用的方法以及用于实现该方法的系统和装置。 用户驻留的非第三代合作伙伴计划(3GPP)接入网络的接入网络信息被绑定到用户的AV,使得当用户通过非3GPP接入网络访问演进分组系统(EPS)时, 即使违反非3GPP接入网络中的实体,或者违反连接到非信任非3GPP接入网络的演进分组数据网关(ePDG),则被盗AV不能通过以下方式应用于其他非3GPP接入网络 攻击者

    Power module and circuit board assembly thereof
    40.
    发明授权
    Power module and circuit board assembly thereof 有权
    电源模块及其电路板组件

    公开(公告)号:US08564394B2

    公开(公告)日:2013-10-22

    申请号:US13408631

    申请日:2012-02-29

    IPC分类号: H01F5/00

    摘要: A power module mounted on a system board comprises a printed circuit board having an extension part, at least one primary winding coil disposed on a first side of the extension part. The at least one primary winding coil is disposed at a primary side of the power module. The power module further comprises a PCB winding formed on the extension part at a secondary side of the power module, a first magnetic core assembly, and a connector. The first magnetic core assembly comprises a first magnetic part and a second magnetic part. The at least one primary winding coil and the extension part are enclosed between the first magnetic part and the second magnetic part.

    摘要翻译: 安装在系统板上的功率模块包括具有延伸部分的印刷电路板,设置在延伸部分的第一侧上的至少一个初级绕组线圈。 所述至少一个初级绕组线圈设置在所述功率模块的初级侧。 功率模块还包括形成在功率模块的次级侧的延伸部分上的PCB绕组,第一磁芯组件和连接器。 第一磁芯组件包括第一磁性部分和第二磁性部分。 所述至少一个初级绕组线圈和所述延伸部分被封装在所述第一磁性部分和所述第二磁性部分之间。