FinFET layout generation
    31.
    发明授权
    FinFET layout generation 失效
    FinFET布局生成

    公开(公告)号:US06662350B2

    公开(公告)日:2003-12-09

    申请号:US09683631

    申请日:2002-01-28

    IPC分类号: G06F1750

    摘要: A method and system for generating a set of FinFET shapes. The method and system locate a gate in an FET layout. The set of FinFET shapes is generated coincident with the gate. The method and system can further create a FinFET layout by modifying the FET layout to include the set of FinFET shapes.

    摘要翻译: 一种用于产生一组FinFET形状的方法和系统。 该方法和系统在FET布局中定位栅极。 产生与栅极一致的一组FinFET形状。 该方法和系统可以通过修改FET布局以包括FinFET形状集合来进一步创建FinFET布局。

    Auto correction of error checked simulated printed images
    32.
    发明授权
    Auto correction of error checked simulated printed images 失效
    错误的自动校正检查模拟打印的图像

    公开(公告)号:US06425112B1

    公开(公告)日:2002-07-23

    申请号:US09335305

    申请日:1999-06-17

    IPC分类号: E06F1750

    CPC分类号: G03F1/36 G06F17/5081

    摘要: A method and computer system are provided for checking integrated circuit designs for design rule violations. The method may include generating a working design data set, creating a wafer image data set, comparing the wafer image data set to the design rules to produce an error list and automatically altering the working design data set when the comparing indicates a design rule violation. The method further automatically repeats the creating, the comparing and the automatically altering until no design rule violations occur or no solution to the errors exists.

    摘要翻译: 提供了一种用于检查设计规则违规的集成电路设计的方法和计算机系统。 该方法可以包括生成工作设计数据集,创建晶片图像数据集,将晶片图像数据集与设计规则进行比较以产生错误列表,并且当比较指示设计规则违反时自动改变工作设计数据集。 该方法进一步自动重复创建,比较和自动更改,直到没有设计规则违规发生或没有解决方案存在错误。

    Method of etch bias proximity correction
    33.
    发明授权
    Method of etch bias proximity correction 失效
    蚀刻偏置接近校正方法

    公开(公告)号:US06395438B1

    公开(公告)日:2002-05-28

    申请号:US09756540

    申请日:2001-01-08

    IPC分类号: G03F900

    CPC分类号: G03F1/36 G03F1/80 G03F7/70433

    摘要: A method for including etch bias corrections in pre-processing of integrated circuit design data to compensate for deviations introduced during lithographic printing and etching. The design data is segmented, and etch bias corrections are applied to the segments based on their proximity to adjacent design features. Adjusted or corrected design data is produced which may be used to create a mask which includes etch bias corrections for better fidelity and reproduction of the original design in the etching step. Etch bias corrections may also be applied based upon characteristics of regions defined in the design, or on a pattern density of the design.

    摘要翻译: 一种在集成电路设计数据的预处理中包括蚀刻偏差校正以补偿在平版印刷和蚀刻期间引入的偏差的方法。 设计数据被分段,并且基于它们与相邻设计特征的接近度,将蚀刻偏差校正应用于段。 产生调整或校正的设计数据,其可用于创建掩模,该掩模包括用于在蚀刻步骤中更好保真度和再现原始设计的蚀刻偏差校正。 也可以基于设计中定义的区域的特征或设计的图案密度来应用蚀刻偏差校正。

    Method of modifying a microchip layout data set to generate a predicted mask printed data set
    34.
    发明授权
    Method of modifying a microchip layout data set to generate a predicted mask printed data set 失效
    修改微芯片布局数据集以产生预测的掩模印刷数据集的方法

    公开(公告)号:US06261724B1

    公开(公告)日:2001-07-17

    申请号:US09334367

    申请日:1999-06-16

    IPC分类号: G03F900

    摘要: A method is presented here that enables one to improve the prediction for the printed structures of circuit patterns in a microchip, thereby potentially aiding in the design of the microchip circuitry. This method comprises the steps of determining, by applying process bias and corner curvature rules to a real mask image, a simulated structure for the mask used in optical projection lithography; and determining, by applying optical and process proximity correction rules to said simulated mask structure, a more accurate prediction for the structures printed on the wafer. Preferably the simulated mask structure is determined by applying a symmetric bias consistent with a mask build process to the real mask image, adjusting predetermined features of the real mask image such as corners or narrow lines, and applying a reverse symmetric bias to the adjusted real mask image.

    摘要翻译: 这里呈现出一种可以改进对微芯片中电路图案的印刷结构的预测的方法,从而有助于微芯片电路的设计。 该方法包括以下步骤:通过将光学投影光刻中使用的掩模的模拟结构应用于实际掩模图像来确定加工偏压和拐角曲率规则; 以及通过对所述模拟掩模结构应用光学和过程接近校正规则来确定印刷在晶片上的结构的更准确的预测。 优选地,通过将​​与掩模构建处理一致的对称偏置应用于真实掩模图像来确定模拟掩模结构,调整真实掩模图像的预定特征,例如拐角或窄线,以及将反向对称偏压施加到经调整的真实掩模 图片。

    Transmission control mask utilized to reduce foreshortening effects
    35.
    发明授权
    Transmission control mask utilized to reduce foreshortening effects 失效
    传输控制面具用于减少缩短效果

    公开(公告)号:US06258490B1

    公开(公告)日:2001-07-10

    申请号:US09350863

    申请日:1999-07-09

    IPC分类号: G03F900

    CPC分类号: G03F1/50 G03F1/36

    摘要: A transmission controlled mask (TCM) for providing effective and accurate printing of images on a semiconductor wafer is defined. The transmission controlled mask (TCM) of the present invention includes opaque regions, clear regions, and transmission controlled (TC) regions, each region have different transmittance for reducing and/or eliminating the foreshortening which occurs in image printing. By employing the TCM of the present invention and adjusting the exposure time, images of lines and holes may be printed correctly with the same mask. The TCM of the present invention comprises a quartz substrate having a carbon layer and a chrome layer deposited on its surface.

    摘要翻译: 定义了用于在半导体晶片上提供有效和准确的图像打印的传输控制掩模(TCM)。 本发明的透射控制掩模(TCM)包括不透明区域,透明区域和透射控制(TC)区域,每个区域具有不同的透射率,用于减少和/或消除在图像打印中发生的缩短。 通过采用本发明的TCM并调整曝光时间,可以用相同的掩模正确地印刷线和孔的图像。 本发明的TCM包括在其表面上沉积有碳层和铬层的石英基底。