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公开(公告)号：US08935582B2
公开(公告)日：2015-01-13
申请号：US13460407
申请日：2012-04-30
申请人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
发明人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318525 , G01R31/31853 , G01R31/318533 , G01R31/318544 , G01R31/318569
摘要： Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.
摘要翻译： 所公开的技术的实施例包括可用于改进扫描链测试模式生成和扫描链故障诊断解析的基于软件的技术。 例如，某些实施例可用于产生能够将扫描链缺陷隔离成单个扫描单元的高质量链诊断测试图案。 这样的实施例可用于产生“完整”测试集，即，能够将故障扫描链中的任何扫描链缺陷分离到单个扫描单元的一组链诊断测试模式。
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公开(公告)号：US08615695B2
公开(公告)日：2013-12-24
申请号：US11818440
申请日：2007-06-13
申请人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
发明人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
CPC分类号： G01R31/3177 , G01R31/318525 , G01R31/318541
摘要： A dictionary-based scan chain fault detector includes a dictionary with fault signatures computed for scan cells in the scan chain. Entries in the fault dictionary are compared with failures in the failure log to identify a faulty scan cell. In one embodiment a single fault in a scan chain is identified. In another embodiment, a last fault and a first fault in a scan chain are identified.
摘要翻译： 基于字典的扫描链故障检测器包括为扫描链中的扫描单元计算的具有故障签名的字典。 将故障字典中的条目与故障日志中的故障进行比较，以识别故障扫描单元。 在一个实施例中，识别扫描链中的单个故障。 在另一个实施例中，识别扫描链中的最后故障和第一故障。
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公开(公告)号：US08438438B2
公开(公告)日：2013-05-07
申请号：US12948460
申请日：2010-11-17
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318569
摘要： Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.
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公开(公告)号：US08301414B2
公开(公告)日：2012-10-30
申请号：US11772648
申请日：2007-07-02
申请人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
发明人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
CPC分类号： G01R31/318547 , G06F11/267
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media comprising lists of fault candidates identified by any of the disclosed methods or circuit descriptions created or modified by the disclosed methods are provided.
摘要翻译： 本文公开了用于执行故障诊断的方法，装置和系统。 在某些公开的实施例中，提供了用于从压缩测试响应诊断故障的方法。 例如，在一个示例性实施例中，接收至少部分基于扫描的测试电路和压实器的电路描述，用于压缩在待测电路中捕获的测试响应。 确定由压实机对被测电路中捕获的测试响应执行的变换功能。 用于评估未压缩测试响应的诊断程序被修改为并入其中的变换功能的修改的诊断过程。 还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。 同样地，提供了包括通过由所公开的方法创建或修改的任何公开的方法或电路描述所识别的故障候选列表的计算机可读介质。
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公开(公告)号：US20110126064A1
公开(公告)日：2011-05-26
申请号：US12948460
申请日：2010-11-17
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/318569
摘要： Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.
摘要翻译： 使用本文描述的各种方法，系统和装置的实施例，可以在存在有限故障循环的情况下增强链或逻辑诊断分辨率。 例如，可以根据诊断覆盖率对图案集进行排序，这可以用于测量图案集的链或逻辑诊断。 基于引脚的诊断技术也可用于分析有限的故障数据。
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36.发明授权公开(公告)号：US07721174B2
公开(公告)日：2010-05-18
申请号：US10985539
申请日：2004-11-09
摘要： A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.
摘要翻译： 公开了一种用于测试嵌入式同步存储器的测试电路。 BIST控制器用于寻址存储器并提供与存储器输出进行比较的参考数据。 流水线寄存器用于允许BIST控制器在每个时钟周期内执行读取和/或写操作。 在一个方面，BIST控制器包括参考数据电路，其存储或产生用于与存储器输出进行比较的数据。 流水线寄存器位于参考数据电路之前或参考数据电路和比较电路之间。 另外的流水线寄存器可以位于比较捕捉电路和比较电路之间。 流水线注册使得BIST控制器在开始下一次读取或写入之前不必等待读取完成。 为了减少所需的流水线寄存器数量，负边缘BIST控制器可以与正边沿存储器一起使用，反之亦然。
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公开(公告)号：US07487419B2
公开(公告)日：2009-02-03
申请号：US11305849
申请日：2005-12-16
申请人： Nilanjan Mukherjee , Jay Jahangiri , Ronald Press , Wu-Tung Cheng
发明人： Nilanjan Mukherjee , Jay Jahangiri , Ronald Press , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318572 , G01R31/318583
摘要： Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.
摘要翻译： 公开了使用一个或多个边界扫描单元测试集成电路的方法，装置和系统。 方法，装置和系统可以用于例如通过一个或多个边界扫描单元应用速度测试图案。 例如，在一个示例性非限制性实施例中，公开了一种电路，其包括耦合到被测电路的主输入端口或主输出端口的一个或多个边界扫描单元。 电路还包括配置成将测试控制信号施加到一个或多个边界扫描单元的边界扫描单元控制器。 在该实施例中，控制器被配置为在操作模式下操作，由此控制器将测试控制信号施加到对应于用于控制电路的一个或多个内部扫描链的测试控制信号的一个或多个边界扫描单元 测试中测试。 该示例性实施例的控制信号包括在边界扫描单元控制器之外产生的一个速度 - 时钟信号。
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公开(公告)号：US07296249B2
公开(公告)日：2007-11-13
申请号：US10961760
申请日：2004-10-07
CPC分类号： G01R31/318547
摘要： Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to propagate a desired test value to the control point. The integrated circuit design is modified to include circuit components configured to load the scan cells in the integrated circuit design with the set of fixed values during a test phase. The one or more scan cells may be identified by justifying the control point to the scan cells, thereby determining values that the scan cells must output in order to drive the control point to the desired test value. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or computer-readable design information for any of the disclosed apparatus are also disclosed.
摘要翻译： 公开了用于测试集成电路的各种新的和非显而易见的装置和方法。 在一个示例性实施例中，在集成电路设计中选择控制点。 识别集成电路设计中的扫描单元，其可以加载一组固定值，以将期望的测试值传播到控制点。 集成电路设计被修改为包括配置成在测试阶段期间以集合的固定值在集成电路设计中加载扫描单元的电路组件。 可以通过将控制点对准扫描单元来识别一个或多个扫描单元，从而确定扫描单元必须输出的值，以便将控制点驱动到期望的测试值。 还公开了包括计算机可执行指令的计算机可读介质，所述计算机可执行指令用于使计算机执行任何所公开的方法或任何所公开的设备的计算机可读设计信息。
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39.发明申请公开(公告)号：US20050066247A1
公开(公告)日：2005-03-24
申请号：US10985539
申请日：2004-11-09
申请人： Wu-Tung Cheng , Christopher Hill , Omar Kebichi
发明人： Wu-Tung Cheng , Christopher Hill , Omar Kebichi
摘要： A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.
摘要翻译： 公开了一种用于测试嵌入式同步存储器的测试电路。 BIST控制器用于寻址存储器并提供与存储器输出进行比较的参考数据。 流水线寄存器用于允许BIST控制器在每个时钟周期内执行读取和/或写操作。 在一个方面，BIST控制器包括参考数据电路，其存储或产生用于与存储器输出进行比较的数据。 流水线寄存器位于参考数据电路之前或参考数据电路和比较电路之间。 另外的流水线寄存器可以位于比较捕捉电路和比较电路之间。 流水线注册使得BIST控制器在开始下一次读取或写入之前不必等待读取完成。 为了减少所需的流水线寄存器数量，负边缘BIST控制器可以与正边沿存储器一起使用，反之亦然。
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40.发明授权公开(公告)号：US06829728B2
公开(公告)日：2004-12-07
申请号：US09800092
申请日：2001-03-05
IPC分类号： G06F1100
摘要： A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.
摘要翻译： 公开了一种用于测试嵌入式同步存储器的测试电路。 BIST控制器用于寻址存储器并提供与存储器输出进行比较的参考数据。 流水线寄存器用于允许BIST控制器在每个时钟周期内执行读取和/或写操作。 在一个方面，BIST控制器包括参考数据电路，其存储或产生用于与存储器输出进行比较的数据。 流水线寄存器位于参考数据电路之前或参考数据电路和比较电路之间。 另外的流水线寄存器可以位于比较捕捉电路和比较电路之间。 流水线注册使得BIST控制器在开始下一次读取或写入之前不必等待读取完成。 为了减少所需的流水线寄存器数量，负边缘BIST控制器可以与正边沿存储器一起使用，反之亦然。
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