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    SPIKE NEURAL NETWORK CIRCUIT INCLUDING INPUT SPIKE DETECTING CIRCUIT AND OPERATING METHOD THEREOF
    33.
    发明公开
    SPIKE NEURAL NETWORK CIRCUIT INCLUDING INPUT SPIKE DETECTING CIRCUIT AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20230385618A1

    公开(公告)日：2023-11-30

    申请号：US18307196

    申请日：2023-04-26

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kwang IL OH ,  Byung-Do YANG ,  Dongwon LEE ,  Jae-Jin LEE

    IPC: G06N3/049 ,  G06N3/063

    CPC classification number: G06N3/049 ,  G06N3/063

    Abstract: Disclosed is a spike neural network circuit including a synaptic circuit including synapses arranged in rows and columns, an axon circuit that generates a first input spike signal to be provided to a first row among the rows, and a second input spike signal to be provided to a second row among the rows, an input spike detecting circuit that generates an enable signal when detecting a pulse from at least one of the first input spike signal and the second input spike signal, and a first neuron circuit that compares a voltage level of a first accumulated signal, which is output from a first column among the columns, with a threshold voltage level in response to the enable signal, and outputs a first output spike signal when the voltage level of the first accumulated signal exceeds the threshold voltage level.

    SYSTEM-ON-CHIP AUTOMATIC DESIGN DEVICE AND OPERATION METHOD THEREOF
    36.
    发明申请
    SYSTEM-ON-CHIP AUTOMATIC DESIGN DEVICE AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20210182462A1

    公开(公告)日：2021-06-17

    申请号：US17116637

    申请日：2020-12-09

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kyuseung HAN ,  Sukho LEE ,  Jae-Jin LEE

    IPC: G06F30/331 ,  G06F13/12

    Abstract: Disclosed is a method of operating a system-on-chip automatic design device. The system-on-chip automatic design device includes a first synthesizer and a second synthesizer. The method includes generating a first code, based on information of a first signal and information of a second signal that are used in a first IP (Intellectual Property) block, classifying a first signal code corresponding to the first signal and a second signal code corresponding to the second signal from the first code, synthesizing, through the first synthesizer, a first communication architecture configured to transmit the first signal, based on the classified first signal code, and synthesizing, through the second synthesizer, a second communication architecture configured to transmit the second signal based on the classified second signal code.

    SPIKE NEURAL NETWORK CIRCUIT INCLUDING RADIATION SOURCE
    38.
    发明申请
    SPIKE NEURAL NETWORK CIRCUIT INCLUDING RADIATION SOURCE 审中-公开

    公开(公告)号：US20190311244A1

    公开(公告)日：2019-10-10

    申请号：US16377983

    申请日：2019-04-08

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kwang IL OH ,  Byounggun CHOI ,  Tae Wook KANG ,  Sung Eun KIM ,  Seong Mo PARK ,  Jae-Jin LEE

    IPC: G06N3/04 ,  G06N3/063

    Abstract: Provided is a spike neural network circuit. The spike neural network circuit includes an axon configured to generate an input spike signal, a synapse including a first transistor for outputting a current according to a weight and a second transistor connected to the first transistor and outputting the current according to an input spike signal, a neuron configured to compare a value according to the current output from the synapse with a reference value and generate an output spike signal based on a comparison result, and a radiation source attached to a substrate on which the synapse is formed, configured to output radiation particles to the synapse, and configured to increase magnitudes of threshold voltages of the first and second transistors of the synapse.

    GRAPHICS PROCESSING UNIT AND OPERATION METHOD THEREOF
    40.
    发明申请
    GRAPHICS PROCESSING UNIT AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190179397A1

    公开(公告)日：2019-06-13

    申请号：US16165878

    申请日：2018-10-19

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Sukho LEE ,  Jae-Jin LEE ,  Kyuseung HAN

    IPC: G06F1/32 ,  G06F1/08 ,  G06F1/28 ,  G06T1/20

    Abstract: Provided is a graphics processing unit and an operation method thereof. The graphics processing unit includes a plurality of cores in which a delay time between an input and an output decreases according to an increase of a temperature, a temperature monitoring and sorting circuit configured to monitor a temperature of each of the plurality of cores, and a controller configured to control a clock frequency and a power supply of the plurality of cores based on a drivable clock frequency of a core having the lowest temperature among temperatures of each of the plurality of monitored cores.

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