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公开(公告)号:US20060294341A1
公开(公告)日:2006-12-28
申请号:US11165757
申请日:2005-06-23
申请人: Erich Plondke , William Anderson , Lucian Codrescu
发明人: Erich Plondke , William Anderson , Lucian Codrescu
IPC分类号: G06F12/00
CPC分类号: G06F9/4812 , G06F12/1027 , Y02D10/13 , Y02D10/24
摘要: A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.
摘要翻译: 共享翻译后备缓冲方法包括:当遇到异常/中断时,将存储在第一选定寄存器组中的数据保存到存储器中线程特定区域的预定部分,重新启用异常和可选中断,解决原因 异常/中断,同时安全地允许另一个异常,并将保存的数据恢复到第一选定的寄存器组。
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32.
公开(公告)号:US07676647B2
公开(公告)日:2010-03-09
申请号:US11506584
申请日:2006-08-18
申请人: Lucian Codrescu , Erich Plondke , Taylor Simpson
发明人: Lucian Codrescu , Erich Plondke , Taylor Simpson
IPC分类号: G06F15/00
CPC分类号: G06F9/30101 , G06F9/30021 , G06F9/30094 , G06F9/3885
摘要: A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.
摘要翻译: 公开了一种处理器装置,其包括具有用于标量和矢量操作的组合条件码寄存器的寄存器文件。 处理器设备利用组合条件码寄存器进行标量和矢量操作。 此外,比较操作可以将结果位存储在组合条件码寄存器中,并且条件操作可以利用组合条件码寄存器位来评估条件。
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公开(公告)号:US07398371B2
公开(公告)日:2008-07-08
申请号:US11165757
申请日:2005-06-23
CPC分类号: G06F9/4812 , G06F12/1027 , Y02D10/13 , Y02D10/24
摘要: A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.
摘要翻译: 共享翻译后备缓冲方法包括:当遇到异常/中断时,将存储在第一选定寄存器组中的数据保存到存储器中线程特定区域的预定部分,重新启用异常和可选中断,解决原因 异常/中断,同时安全地允许另一个异常,并将保存的数据恢复到第一选定的寄存器组。
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公开(公告)号:US08281111B2
公开(公告)日:2012-10-02
申请号:US12236067
申请日:2008-09-23
IPC分类号: G06F9/305
CPC分类号: G06F9/30018 , G06F7/584 , G06F9/30003 , G06F9/30032
摘要: A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further includes determining a parity value of the intermediate data, shifting the source data, and entering the parity value of the intermediate data into a data field of the shifted source data to produce resultant data.
摘要翻译: 公开了一种执行线性反馈移位指令的系统和方法。 在特定实施例中,该方法包括通过接收源数据并对源数据和参考数据执行逐位逻辑运算来执行处理器处的指令以产生中间数据。 该方法还包括确定中间数据的奇偶校验值,移位源数据,并将中间数据的奇偶校验值输入到移位的源数据的数据字段中,以产生结果数据。
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公开(公告)号:US20100077187A1
公开(公告)日:2010-03-25
申请号:US12236067
申请日:2008-09-23
IPC分类号: G06F9/305
CPC分类号: G06F9/30018 , G06F7/584 , G06F9/30003 , G06F9/30032
摘要: A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further includes determining a parity value of the intermediate data, shifting the source data, and entering the parity value of the intermediate data into a data field of the shifted source data to produce resultant data.
摘要翻译: 公开了一种执行线性反馈移位指令的系统和方法。 在特定实施例中,该方法包括通过接收源数据并对源数据和参考数据执行逐位逻辑运算来执行处理器处的指令以产生中间数据。 该方法还包括确定中间数据的奇偶校验值,移位源数据,并将中间数据的奇偶校验值输入到移位的源数据的数据字段中,以产生结果数据。
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36.
公开(公告)号:US20080046683A1
公开(公告)日:2008-02-21
申请号:US11506584
申请日:2006-08-18
申请人: Lucian Codrescu , Erich Plondke , Taylor Simpson
发明人: Lucian Codrescu , Erich Plondke , Taylor Simpson
IPC分类号: G06F15/76
CPC分类号: G06F9/30101 , G06F9/30021 , G06F9/30094 , G06F9/3885
摘要: A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.
摘要翻译: 公开了一种处理器装置,其包括具有用于标量和矢量操作的组合条件码寄存器的寄存器文件。 处理器设备利用组合条件码寄存器进行标量和矢量操作。 此外,比较操作可以将结果位存储在组合条件码寄存器中,并且条件操作可以利用组合条件码寄存器位来评估条件。
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