公开(公告)号：US07365728B2

公开(公告)日：2008-04-29

申请号：US10895891

申请日：2004-07-22

申请人： Sachio Tsujino ,  Shinya Takahashi

发明人： Sachio Tsujino ,  Shinya Takahashi

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G09G2310/0267 ,  G09G2310/08 ,  G09G2330/021

摘要： A display device is provided with a shift register having a plurality of bistable circuits, each of the bistable circuits being connected to a corresponding scanning line. An RS flip-flop circuit provided in each of the bistable circuits functions as a memory portion for discriminating a start position of a display region for partial display. When partial display is carried out, first, only the RS flip-flop circuit corresponding to the start position of the display region is put into the set state, that is, only the bistable circuit corresponding to the start position of the display region is put into the set state. Moreover, the scanning lines that are connected to the bistable circuits from the start position to the end position are driven sequentially. During this, only the bistable circuit corresponding to the start position is kept in the set state, and the other bistable circuits are kept in the reset state.

摘要翻译： 显示装置设置有具有多个双稳态电路的移位寄存器，每个双稳态电路连接到对应的扫描线。 设置在每个双稳态电路中的RS触发器电路用作用于区分用于部分显示的显示区域的开始位置的存储部分。 当进行部分显示时，首先，仅将与显示区域的开始位置相对应的RS触发器电路置于设定状态，即仅放置与显示区域的开始位置对应的双稳态电路 进入设定状态。 此外，从起始位置到结束位置连接到双稳态电路的扫描线被依次驱动。 在此期间，只有与开始位置相对应的双稳电路保持在设定状态，其他双稳态电路保持在复位状态。

公开(公告)号：US20080036753A1

公开(公告)日：2008-02-14

申请号：US11882533

申请日：2007-08-02

申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2310/0213 ,  G09G2310/0232 ,  G09G2310/027 ,  G09G2310/0283 ,  G09G2310/0297 ,  G09G2310/04 ,  G09G2320/0214 ,  G09G2320/10 ,  G09G2330/021

摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.

摘要翻译： 用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于非显示区域的电压VB或电压VW， 不仅在第一帧中显示，而且在预定数量的帧中显示一次。 换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。 因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷， 可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时 限制功耗。

公开(公告)号：US08780101B2

公开(公告)日：2014-07-15

申请号：US13391654

申请日：2010-07-12

申请人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

发明人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

IPC分类号： G09G5/00

CPC分类号： H01L27/14643 ,  G06F3/0412 ,  G06F3/042 ,  H04N5/357

摘要： By reducing the potential drop of a storage node that occurs due to feedthrough, the capacitance of a storage capacitor is reduced and sensor sensitivity is improved. In a photosensor, the first terminal of a storage capacitor (C2) and the gate of a MOS transistor (M1), which outputs a signal in accordance with the potential of a storage node (N2), are connected to the storage node (N2). A forward biased pulse voltage is supplied to the anode of a first photodiode (DS) in a reset period, and a reverse biased voltage is supplied to the anode of the first photodiode in a storage period and a readout period. A reverse biased voltage is supplied to the anode of a second photodiode (DM) in all operation periods. A voltage that keeps the potential of the storage node lower than the threshold value of the MOS transistor (M1) is supplied to the second terminal of the storage capacitor in the reset period and the storage period, and a voltage that thrusts the potential of the storage node (N2) upward to the threshold value of the MOS transistor (M1) or higher is supplied to the second terminal of the storage capacitor in the readout period.

摘要翻译： 通过减少由于馈通而发生的存储节点的潜在下降，存储电容器的电容降低并且传感器灵敏度得到改善。 在光电传感器中，根据存储节点（N2）的电位输出信号的存储电容器（C2）的第一端子和MOS晶体管（M1）的栅极连接到存储节点（N2 ）。 在复位周期中将正向偏置脉冲电压提供给第一光电二极管（DS）的阳极，并且在存储周期和读出周期中向第一光电二极管的阳极提供反向偏置电压。 在所有操作周期中，向第二光电二极管（DM）的阳极提供反向偏置电压。 在复位期间和保存期间，保持存储节点的电位低于MOS晶体管（M1）的阈值的电压被提供给存储电容器的第二端子，并且将电压 存储节点（N2）向上升到MOS晶体管（M1）或更高的阈值，在读出期间提供给存储电容器的第二端。

公开(公告)号：US20130162602A1

公开(公告)日：2013-06-27

申请号：US13810214

申请日：2011-04-25

申请人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Sachio Tsujino ,  Hiroaki Sugiyama ,  Ichiroh Shiraki

发明人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Sachio Tsujino ,  Hiroaki Sugiyama ,  Ichiroh Shiraki

IPC分类号： G06F3/042

CPC分类号： H01L27/14601 ,  G06F3/0412 ,  G06F3/042 ,  G09G3/3406 ,  G09G3/3648

摘要： A plurality of sensor circuits each including an optical sensor and a charge retention transistor each provided between a reset line and an accumulation node are arranged in a pixel region of a display device. In a sensing period, a LOW-level voltage is applied as a reset cancellation voltage to the reset line RSTa, and a HIGH-level voltage is applied to a control line CLKa to control the charge retention transistor to be in an ON state. In a period other than the sensing period, the LOW-level voltage is applied to the control line CLKa to control the charge retention transistor to be in an OFF state, and the HIGH-level voltage is applied as a retention voltage to the reset line RSTa. Thus, a drain-source voltage Vds of the charge retention transistor is lowered, a leakage current through the charge retention transistor is reduced, and a light detection accuracy is enhanced. A substantially middle voltage between a reset voltage and a voltage at an accumulation node at the sensing of a maximum amount of light may be used as the retention voltage.

摘要翻译： 在显示装置的像素区域中配置有各自包括设置在复位线和累积节点之间的光学传感器和电荷保持晶体管的多个传感器电路。 在感测期间，将低电平电压作为复位消除电压施加到复位线RSTa，并且将高电平电压施加到控制线CLKa以将电荷保持晶体管控制在导通状态。 在感测期间以外的期间，将低电平电压施加到控制线CLKa，以将电荷保持晶体管控制为截止状态，并且将高电平电压作为保持电压施加到复位线 RSTa。 因此，电荷保持晶体管的漏极 - 源极电压Vds降低，通过电荷保持晶体管的漏电流减小，光检测精度提高。 可以使用在检测最大光量时在复位电压和累积节点处的电压之间的实质中等电压作为保持电压。

公开(公告)号：US08130216B2

公开(公告)日：2012-03-06

申请号：US11882533

申请日：2007-08-02

申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2310/0213 ,  G09G2310/0232 ,  G09G2310/027 ,  G09G2310/0283 ,  G09G2310/0297 ,  G09G2310/04 ,  G09G2320/0214 ,  G09G2320/10 ,  G09G2330/021

摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.

摘要翻译： 用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD2写入用于不显示的电压VB或电压VW ，不仅在第一帧中，而且在预定数量的帧中也是一次。 换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。 因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷， 可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时 限制功耗。

公开(公告)号：US20090121998A1

公开(公告)日：2009-05-14

申请号：US12087887

申请日：2006-11-30

申请人： Hiroyuki Ohkawa ,  Yuhichiroh Murakami ,  Sachio Tsujino

发明人： Hiroyuki Ohkawa ,  Yuhichiroh Murakami ,  Sachio Tsujino

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2310/0245 ,  G09G2310/0286 ,  G09G2330/027 ,  G11C19/28

摘要： A liquid crystal display apparatus (1) wherein the shift registers of a source driver (4) are configured by use of asynchronous RS flip-flops in which an active input to a set input terminal has a higher priority than an active input to a reset terminal. In a second mode of operation, first and second clock signals and a start pulse are fixed at high levels, thereby performing discharges from all the pixels (PIX) of a liquid crystal panel (2).

摘要翻译： 一种液晶显示装置（1），其中源驱动器（4）的移位寄存器通过使用异步RS触发器来配置，其中对设置输入端子的有效输入具有比复位的有效输入更高的优先级 终奌站。 在第二操作模式中，第一和第二时钟信号和起始脉冲被固定为高电平，从而执行来自液晶面板（2）的所有像素（PIX）的放电。

公开(公告)号：US20050017942A1

公开(公告)日：2005-01-27

申请号：US10895891

申请日：2004-07-22

申请人： Sachio Tsujino ,  Shinya Takahashi

发明人： Sachio Tsujino ,  Shinya Takahashi

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  H01L51/50 ,  H05B33/14

CPC分类号： G09G3/20 ,  G09G2310/0267 ,  G09G2310/08 ,  G09G2330/021

摘要： A display device is provided with a shift register having a plurality of bistable circuits, each of the bistable circuits being connected to a corresponding scanning line. An RS flip-flop circuit provided in each of the bistable circuits functions as a memory portion for discriminating a start position of a display region for partial display. When partial display is carried out, first, only the RS flip-flop circuit corresponding to the start position of the display region is put into the set state, that is, only the bistable circuit corresponding to the start position of the display region is put into the set state. Moreover, the scanning lines that are connected to the bistable circuits from the start position to the end position are driven sequentially. During this, only the bistable circuit corresponding to the start position is kept in the set state, and the other bistable circuits are kept in the reset state.

摘要翻译： 显示装置设置有具有多个双稳态电路的移位寄存器，每个双稳态电路连接到相应的扫描线。 设置在每个双稳态电路中的RS触发器电路用作用于区分用于部分显示的显示区域的开始位置的存储部分。 当进行部分显示时，首先，仅将与显示区域的开始位置相对应的RS触发器电路置于设定状态，即仅放置与显示区域的开始位置对应的双稳态电路 进入设定状态。 此外，从起始位置到结束位置连接到双稳态电路的扫描线被依次驱动。 在此期间，只有与开始位置相对应的双稳电路保持在设定状态，其他双稳态电路保持在复位状态。