公开(公告)号：US20120154354A1

公开(公告)日：2012-06-21

申请号：US13391654

申请日：2010-07-12

申请人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

发明人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

IPC分类号： G09G5/02 ,  G01J1/46

CPC分类号： H01L27/14643 ,  G06F3/0412 ,  G06F3/042 ,  H04N5/357

摘要： By reducing the potential drop of a storage node that occurs due to feedthrough, the capacitance of a storage capacitor is reduced and sensor sensitivity is improved. In a photosensor, the first terminal of a storage capacitor (C2) and the gate of a MOS transistor (M1), which outputs a signal in accordance with the potential of a storage node (N2), are connected to the storage node (N2). A forward biased pulse voltage is supplied to the anode of a first photodiode (DS) in a reset period, and a reverse biased voltage is supplied to the anode of the first photodiode in a storage period and a readout period. A reverse biased voltage is supplied to the anode of a second photodiode (DM) in all operation periods. A voltage that keeps the potential of the storage node lower than the threshold value of the MOS transistor (M1) is supplied to the second terminal of the storage capacitor in the reset period and the storage period, and a voltage that thrusts the potential of the storage node (N2) upward to the threshold value of the MOS transistor (M1) or higher is supplied to the second terminal of the storage capacitor in the readout period.

摘要翻译： 通过减少由于馈通而发生的存储节点的潜在下降，存储电容器的电容降低并且传感器灵敏度得到改善。 在光电传感器中，根据存储节点（N2）的电位输出信号的存储电容器（C2）的第一端子和MOS晶体管（M1）的栅极连接到存储节点（N2 ）。 在复位周期中将正向偏置脉冲电压提供给第一光电二极管（DS）的阳极，并且在存储周期和读出周期中向第一光电二极管的阳极提供反向偏置电压。 在所有操作周期中，向第二光电二极管（DM）的阳极提供反向偏置电压。 在复位期间和保存期间，保持存储节点的电位低于MOS晶体管（M1）的阈值的电压被提供给存储电容器的第二端子，并且将电压 存储节点（N2）向上升到MOS晶体管（M1）或更高的阈值，在读出期间提供给存储电容器的第二端。

公开(公告)号：US20100259565A1

公开(公告)日：2010-10-14

申请号：US12733884

申请日：2008-06-19

申请人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiro Shiraki ,  Shuji Nishi ,  Sachio Tsujino

发明人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiro Shiraki ,  Shuji Nishi ,  Sachio Tsujino

IPC分类号： G09G5/10

CPC分类号： G09G3/20 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2001/13606 ,  G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2330/021 ,  H01L27/124

摘要： The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal.In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.

摘要翻译： 本发明的目的在于提供一种能够降低采样电路的电路规模的单片驱动型显示装置，并且通过用外部提供的视频信号直接驱动源极驱动器来保持低功耗。 在具有用于显示视频的显示部分和用于驱动形成在同一绝缘基板上的显示部分的电路的单片驱动型显示装置中，与外部输入的多个位数据相关联地提供多个采样开关 数字视频信号。 采样开关基于采样信号进行开/关，从而针对每一位数据采样数字视频信号，并将信号转换为并行格式以输出到数据线。 输出的数字视频信号对数据线上的寄生电容进行充电并保持在其中。

公开(公告)号：US07733321B2

公开(公告)日：2010-06-08

申请号：US11543219

申请日：2006-10-05

申请人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

发明人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

IPC分类号： G09G3/36

CPC分类号： G11C19/00 ,  G09G3/20 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

摘要翻译： 移位寄存器包括多级触发器。 作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。 在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入 信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。 通过这种布置，可以防止由于不能重置触发器而引起的电路故障。

公开(公告)号：US07652652B2

公开(公告)日：2010-01-26

申请号：US10705775

申请日：2003-11-12

申请人： Kazuhiro Maeda ,  Sachio Tsujino ,  Hajime Washio ,  Yuhji Asoh

发明人： Kazuhiro Maeda ,  Sachio Tsujino ,  Hajime Washio ,  Yuhji Asoh

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G3/20 ,  G09G3/2011 ,  G09G2310/0297

摘要： The data signal line driving circuit of the present invention is arranged so that data signal line groups, each of which is made up of two data signal lines sequentially disposed, are connected to two video signal lines, each of which allows a two-phased video signal to be forwarded. A shift register SR, a drive switching circuit, and a waveform shaping circuit, that constitute a video signal fetching section, collect the data signal line groups via the two video signal lines as a single block. At this time, the data signal lines are respectively driven so as to fetch the video signal from the video signal lines into the data signal lines of the data signal line groups in each block. Thus, in performing multiphase development, it is possible to provide the data signal line driving circuit which can reduce power consumption in low resolution driving compared with a case of high resolution driving.

摘要翻译： 本发明的数据信号线驱动电路被布置成使得由两条数据信号线构成的数据信号线组连接到两条视频信号线，每条视频信号线允许两相视频 信号被转发。 构成视频信号取出部的移位寄存器SR，驱动切换电路以及波形整形电路通过两个视频信号线收集数据信号线组作为单个块。 此时，分别驱动数据信号线，以将视频信号从视频信号线提取到每个块中的数据信号线组的数据信号线中。 因此，在执行多相显影时，与高分辨率驱动的情况相比，可以提供能够降低分辨率驱动中的功耗的数据信号线驱动电路。

公开(公告)号：US20070242021A1

公开(公告)日：2007-10-18

申请号：US11812461

申请日：2007-06-19

申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

IPC分类号： H03K19/0175

CPC分类号： G09G3/3611 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/018521

摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

公开(公告)号：US07202846B2

公开(公告)日：2007-04-10

申请号：US10440077

申请日：2003-05-15

申请人： Kazuhiro Maeda ,  Sachio Tsujino ,  Keiji Takahashi ,  Hajime Washio

发明人： Kazuhiro Maeda ,  Sachio Tsujino ,  Keiji Takahashi ,  Hajime Washio

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0294 ,  G09G2330/021 ,  G09G2340/0421

摘要： A data signal line drive circuit is provided with: a shift register belonging to a system, whose stages correspond to respective sampling units for driving odd-number-th data signal lines; and a shift register belonging to another system, whose stages correspond to respective sampling units for driving even-number-th data signal lines. On the occasion of low-resolution mode, only either of the shift registers is operated, and in accordance with the outputs from the respective stages of the shift register which has been operated, timing signals, which are supplied to the sampling units corresponding to the stages of both shift registers, are generated. With this arrangement, even if one of input signals each having different signal line resolution is inputted, a signal line drive circuit which consumes a small amount of electric power can be realized, while it is possible to specify the timings of the operation of signal line drive sections for driving signal lines, in accordance with the input signal.

摘要翻译： 数据信号线驱动电路具有：属于系统的移位寄存器，其级对应于用于驱动奇数数据信号线的相应采样单元; 以及属于另一系统的移位寄存器，其级对应于用于驱动第二数据信号线的相应采样单元。 在低分辨率模式的情况下，仅移动寄存器中的任一个被操作，并且根据已经被操作的移位寄存器的各个级的输出，定时信号被提供给对应于 生成两个移位寄存器的阶段。 通过这样的配置，即使输入信号线分辨率不同的输入信号之一，也可以实现消耗少量电力的信号线驱动电路，同时可以规定信号线的动作时序 用于驱动信号线的驱动部分，根据输入信号。

公开(公告)号：US20050175138A1

公开(公告)日：2005-08-11

申请号：US11044003

申请日：2005-01-28

申请人： Eiji Matsuda ,  Yuhichiroh Murakami ,  Sachio Tsujino ,  Hajime Washio

发明人： Eiji Matsuda ,  Yuhichiroh Murakami ,  Sachio Tsujino ,  Hajime Washio

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  G11C19/28 ,  H03K17/693

CPC分类号： G09G3/3688 ,  G11C19/00 ,  G11C19/28

摘要： In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.

摘要翻译： 在本发明的移位寄存器中，每个触发器具有作为故障防止电路的相位差检测部分和波形定时形成部分。 相位差检测部分检测由时钟信号SCK和SCKB之间的相位差引起的重叠波形，并且生成从其重叠​​部分被去除的输出信号A（A 1，A 2，...）。 波形定时形成部输出通过提取在对应的相位差检测部中产生的输出信号A（A 1，A 2，...）的周期而获得的输出信号X（X 1，X 2，...） 当来自相应触发器的输出信号Q（Q 1，Q 2，...）为高时，为高电平。 输出信号X（X 1，X 2，...）在下一阶段设置触发器。 根据上述结构，即使在输入到移位寄存器的两个时钟信号SCK，SCKB彼此相位不同的情况下也可以实现不发生故障的功能，也能正常工作的移位寄存器。 也可以实现具有移位寄存器的显示装置。

公开(公告)号：US08780101B2

公开(公告)日：2014-07-15

申请号：US13391654

申请日：2010-07-12

申请人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

发明人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

IPC分类号： G09G5/00

CPC分类号： H01L27/14643 ,  G06F3/0412 ,  G06F3/042 ,  H04N5/357

摘要： By reducing the potential drop of a storage node that occurs due to feedthrough, the capacitance of a storage capacitor is reduced and sensor sensitivity is improved. In a photosensor, the first terminal of a storage capacitor (C2) and the gate of a MOS transistor (M1), which outputs a signal in accordance with the potential of a storage node (N2), are connected to the storage node (N2). A forward biased pulse voltage is supplied to the anode of a first photodiode (DS) in a reset period, and a reverse biased voltage is supplied to the anode of the first photodiode in a storage period and a readout period. A reverse biased voltage is supplied to the anode of a second photodiode (DM) in all operation periods. A voltage that keeps the potential of the storage node lower than the threshold value of the MOS transistor (M1) is supplied to the second terminal of the storage capacitor in the reset period and the storage period, and a voltage that thrusts the potential of the storage node (N2) upward to the threshold value of the MOS transistor (M1) or higher is supplied to the second terminal of the storage capacitor in the readout period.

摘要翻译： 通过减少由于馈通而发生的存储节点的潜在下降，存储电容器的电容降低并且传感器灵敏度得到改善。 在光电传感器中，根据存储节点（N2）的电位输出信号的存储电容器（C2）的第一端子和MOS晶体管（M1）的栅极连接到存储节点（N2 ）。 在复位周期中将正向偏置脉冲电压提供给第一光电二极管（DS）的阳极，并且在存储周期和读出周期中向第一光电二极管的阳极提供反向偏置电压。 在所有操作周期中，向第二光电二极管（DM）的阳极提供反向偏置电压。 在复位期间和保存期间，保持存储节点的电位低于MOS晶体管（M1）的阈值的电压被提供给存储电容器的第二端子，并且将电压 存储节点（N2）向上升到MOS晶体管（M1）或更高的阈值，在读出期间提供给存储电容器的第二端。

公开(公告)号：US08665255B2

公开(公告)日：2014-03-04

申请号：US12733813

申请日：2008-07-24

申请人： Sachio Tsujino ,  Shuji Nishi ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

发明人： Sachio Tsujino ,  Shuji Nishi ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

IPC分类号： G09G5/00

CPC分类号： H02M3/073

摘要： An object of the present invention is to provide a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. In a booster section (11a), capacitors (C1) and (C2) have their respective first terminals connected with transistors (Q1, Q3) and (Q2, Q4) respectively. Each transistor has its gate terminal supplied with control signals generated in a driver section (11b). The driver section (11b) includes capacitors (C3, C4) connected with input terminals (Ti3, Ti4) for respective supply of clock signals DCK2, DCK2B each having a voltage alternating between −VDD and VDD (VDD represents an input supply voltage from outside), as level-shifted signals of clock signals DCK1, DCK1B which are supplied to second terminals of the capacitors (C1, C2) respectively. In this arrangement, the driver section 11b generates signals each having a voltage alternating between VDD and 3VDD, as the control signals.

摘要翻译： 本发明的目的是提供一种电源电路，其包括使用仅由N沟道晶体管提供的开关元件的电荷泵浦升压器部分，但不具有通过阈值的电压降的问题。 在升压部（11a）中，电容器（C1）和（C2）分别具有与晶体管（Q1，Q3）和（Q2，Q4）相连的各自的第一端子。 每个晶体管的栅极端子提供有在驱动器部分（11b）中产生的控制信号。 驱动器部分（11b）包括与输入端子（Ti3，Ti4）连接的电容器（C3，C4），用于各自提供时钟信号DCK2，DCK2B各自具有在-VDD和VDD之间交替的电压（VDD表示来自外部的输入电源电压 ）作为分别提供给电容器（C1，C2）的第二端子的时钟信号DCK1，DCK1B的电平移位信号。 在这种布置中，驱动器部分11b产生各自具有在VDD和3VDD之间交替的电压的信号作为控制信号。

公开(公告)号：US20130162602A1

公开(公告)日：2013-06-27

申请号：US13810214

申请日：2011-04-25

申请人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Sachio Tsujino ,  Hiroaki Sugiyama ,  Ichiroh Shiraki

发明人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Sachio Tsujino ,  Hiroaki Sugiyama ,  Ichiroh Shiraki

IPC分类号： G06F3/042

CPC分类号： H01L27/14601 ,  G06F3/0412 ,  G06F3/042 ,  G09G3/3406 ,  G09G3/3648

摘要： A plurality of sensor circuits each including an optical sensor and a charge retention transistor each provided between a reset line and an accumulation node are arranged in a pixel region of a display device. In a sensing period, a LOW-level voltage is applied as a reset cancellation voltage to the reset line RSTa, and a HIGH-level voltage is applied to a control line CLKa to control the charge retention transistor to be in an ON state. In a period other than the sensing period, the LOW-level voltage is applied to the control line CLKa to control the charge retention transistor to be in an OFF state, and the HIGH-level voltage is applied as a retention voltage to the reset line RSTa. Thus, a drain-source voltage Vds of the charge retention transistor is lowered, a leakage current through the charge retention transistor is reduced, and a light detection accuracy is enhanced. A substantially middle voltage between a reset voltage and a voltage at an accumulation node at the sensing of a maximum amount of light may be used as the retention voltage.

摘要翻译： 在显示装置的像素区域中配置有各自包括设置在复位线和累积节点之间的光学传感器和电荷保持晶体管的多个传感器电路。 在感测期间，将低电平电压作为复位消除电压施加到复位线RSTa，并且将高电平电压施加到控制线CLKa以将电荷保持晶体管控制在导通状态。 在感测期间以外的期间，将低电平电压施加到控制线CLKa，以将电荷保持晶体管控制为截止状态，并且将高电平电压作为保持电压施加到复位线 RSTa。 因此，电荷保持晶体管的漏极 - 源极电压Vds降低，通过电荷保持晶体管的漏电流减小，光检测精度提高。 可以使用在检测最大光量时在复位电压和累积节点处的电压之间的实质中等电压作为保持电压。