公开(公告)号：US20120154354A1

公开(公告)日：2012-06-21

申请号：US13391654

申请日：2010-07-12

申请人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

发明人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

IPC分类号： G09G5/02 ,  G01J1/46

CPC分类号： H01L27/14643 ,  G06F3/0412 ,  G06F3/042 ,  H04N5/357

摘要： By reducing the potential drop of a storage node that occurs due to feedthrough, the capacitance of a storage capacitor is reduced and sensor sensitivity is improved. In a photosensor, the first terminal of a storage capacitor (C2) and the gate of a MOS transistor (M1), which outputs a signal in accordance with the potential of a storage node (N2), are connected to the storage node (N2). A forward biased pulse voltage is supplied to the anode of a first photodiode (DS) in a reset period, and a reverse biased voltage is supplied to the anode of the first photodiode in a storage period and a readout period. A reverse biased voltage is supplied to the anode of a second photodiode (DM) in all operation periods. A voltage that keeps the potential of the storage node lower than the threshold value of the MOS transistor (M1) is supplied to the second terminal of the storage capacitor in the reset period and the storage period, and a voltage that thrusts the potential of the storage node (N2) upward to the threshold value of the MOS transistor (M1) or higher is supplied to the second terminal of the storage capacitor in the readout period.

摘要翻译： 通过减少由于馈通而发生的存储节点的潜在下降，存储电容器的电容降低并且传感器灵敏度得到改善。 在光电传感器中，根据存储节点（N2）的电位输出信号的存储电容器（C2）的第一端子和MOS晶体管（M1）的栅极连接到存储节点（N2 ）。 在复位周期中将正向偏置脉冲电压提供给第一光电二极管（DS）的阳极，并且在存储周期和读出周期中向第一光电二极管的阳极提供反向偏置电压。 在所有操作周期中，向第二光电二极管（DM）的阳极提供反向偏置电压。 在复位期间和保存期间，保持存储节点的电位低于MOS晶体管（M1）的阈值的电压被提供给存储电容器的第二端子，并且将电压 存储节点（N2）向上升到MOS晶体管（M1）或更高的阈值，在读出期间提供给存储电容器的第二端。

公开(公告)号：US08780101B2

公开(公告)日：2014-07-15

申请号：US13391654

申请日：2010-07-12

申请人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

发明人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

IPC分类号： G09G5/00

CPC分类号： H01L27/14643 ,  G06F3/0412 ,  G06F3/042 ,  H04N5/357

摘要： By reducing the potential drop of a storage node that occurs due to feedthrough, the capacitance of a storage capacitor is reduced and sensor sensitivity is improved. In a photosensor, the first terminal of a storage capacitor (C2) and the gate of a MOS transistor (M1), which outputs a signal in accordance with the potential of a storage node (N2), are connected to the storage node (N2). A forward biased pulse voltage is supplied to the anode of a first photodiode (DS) in a reset period, and a reverse biased voltage is supplied to the anode of the first photodiode in a storage period and a readout period. A reverse biased voltage is supplied to the anode of a second photodiode (DM) in all operation periods. A voltage that keeps the potential of the storage node lower than the threshold value of the MOS transistor (M1) is supplied to the second terminal of the storage capacitor in the reset period and the storage period, and a voltage that thrusts the potential of the storage node (N2) upward to the threshold value of the MOS transistor (M1) or higher is supplied to the second terminal of the storage capacitor in the readout period.

摘要翻译： 通过减少由于馈通而发生的存储节点的潜在下降，存储电容器的电容降低并且传感器灵敏度得到改善。 在光电传感器中，根据存储节点（N2）的电位输出信号的存储电容器（C2）的第一端子和MOS晶体管（M1）的栅极连接到存储节点（N2 ）。 在复位周期中将正向偏置脉冲电压提供给第一光电二极管（DS）的阳极，并且在存储周期和读出周期中向第一光电二极管的阳极提供反向偏置电压。 在所有操作周期中，向第二光电二极管（DM）的阳极提供反向偏置电压。 在复位期间和保存期间，保持存储节点的电位低于MOS晶体管（M1）的阈值的电压被提供给存储电容器的第二端子，并且将电压 存储节点（N2）向上升到MOS晶体管（M1）或更高的阈值，在读出期间提供给存储电容器的第二端。

公开(公告)号：US20120313913A1

公开(公告)日：2012-12-13

申请号：US13581208

申请日：2010-11-24

申请人： Ichiroh Shiraki ,  Kazuhiro Maeda ,  Sachio Tsujino ,  Hiroaki Sugiyama ,  Yousuke Nakagawa

发明人： Ichiroh Shiraki ,  Kazuhiro Maeda ,  Sachio Tsujino ,  Hiroaki Sugiyama ,  Yousuke Nakagawa

IPC分类号： G09G5/00

CPC分类号： G06K9/0004 ,  G06F3/0412 ,  G06K9/00013 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2360/144 ,  G09G2360/147

摘要： Detection signals of respective photo sensor circuits (senS, senD, senON, and senOFF) are activated so as to be output at once for each group of prescribed plural number of sensor rows (LSk) by a row driver (6). Within the prescribed number of sensor rows (LSk), photo sensor circuits (senS, senD, senON, and senOFF) sharing the same power line (SL2, SL5, . . . ) between at least two different sensor rows (LSk) are included. The detection signals of the respective photo sensor circuits (senS, senD, senON, and senOFF) in the prescribed number of sensor rows (senS, senD, senON, and senOFF) are output via mutually different output lines (SL1/SL3, SL4/SL6, . . . ).

摘要翻译： 各光电传感器电路（senS，senD，senON，senOFF）的检测信号被激活，以便通过行驱动器（6）为每组规定的多个传感器行（LSk）一次输出。 在规定数量的传感器行（LSk）内，包括在至少两个不同传感器行（LSk）之间共享同一电力线（SL2，SL5 ...）的光电传感器电路（senS，senD，senON和senOFF） 。 在规定数量的传感器列（senS，senD，senON和senOFF）中的各个光电传感器电路（senS，senD，senON和senOFF）的检测信号通过相互不同的输出线（SL1 / SL3，SL4 / SL6，...）。

公开(公告)号：US20130162602A1

公开(公告)日：2013-06-27

申请号：US13810214

申请日：2011-04-25

申请人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Sachio Tsujino ,  Hiroaki Sugiyama ,  Ichiroh Shiraki

发明人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Sachio Tsujino ,  Hiroaki Sugiyama ,  Ichiroh Shiraki

IPC分类号： G06F3/042

CPC分类号： H01L27/14601 ,  G06F3/0412 ,  G06F3/042 ,  G09G3/3406 ,  G09G3/3648

摘要： A plurality of sensor circuits each including an optical sensor and a charge retention transistor each provided between a reset line and an accumulation node are arranged in a pixel region of a display device. In a sensing period, a LOW-level voltage is applied as a reset cancellation voltage to the reset line RSTa, and a HIGH-level voltage is applied to a control line CLKa to control the charge retention transistor to be in an ON state. In a period other than the sensing period, the LOW-level voltage is applied to the control line CLKa to control the charge retention transistor to be in an OFF state, and the HIGH-level voltage is applied as a retention voltage to the reset line RSTa. Thus, a drain-source voltage Vds of the charge retention transistor is lowered, a leakage current through the charge retention transistor is reduced, and a light detection accuracy is enhanced. A substantially middle voltage between a reset voltage and a voltage at an accumulation node at the sensing of a maximum amount of light may be used as the retention voltage.

摘要翻译： 在显示装置的像素区域中配置有各自包括设置在复位线和累积节点之间的光学传感器和电荷保持晶体管的多个传感器电路。 在感测期间，将低电平电压作为复位消除电压施加到复位线RSTa，并且将高电平电压施加到控制线CLKa以将电荷保持晶体管控制在导通状态。 在感测期间以外的期间，将低电平电压施加到控制线CLKa，以将电荷保持晶体管控制为截止状态，并且将高电平电压作为保持电压施加到复位线 RSTa。 因此，电荷保持晶体管的漏极 - 源极电压Vds降低，通过电荷保持晶体管的漏电流减小，光检测精度提高。 可以使用在检测最大光量时在复位电压和累积节点处的电压之间的实质中等电压作为保持电压。

公开(公告)号：US08305315B2

公开(公告)日：2012-11-06

申请号：US12733884

申请日：2008-06-19

申请人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiro Shiraki ,  Shuji Nishi ,  Sachio Tsujino

发明人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiro Shiraki ,  Shuji Nishi ,  Sachio Tsujino

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2001/13606 ,  G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2330/021 ,  H01L27/124

摘要： The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal.In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.

摘要翻译： 本发明的目的在于提供一种能够降低采样电路的电路规模的单片驱动型显示装置，并且通过用外部提供的视频信号直接驱动源极驱动器来保持低功耗。 在具有用于显示视频的显示部分和用于驱动形成在同一绝缘基板上的显示部分的电路的单片驱动型显示装置中，与外部输入的多个位数据相关联地提供多个采样开关 数字视频信号。 采样开关基于采样信号进行开/关，从而针对每一位数据采样数字视频信号，并将信号转换为并行格式以输出到数据线。 输出的数字视频信号对数据线上的寄生电容进行充电并保持在其中。

公开(公告)号：US20100259565A1

公开(公告)日：2010-10-14

申请号：US12733884

申请日：2008-06-19

申请人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiro Shiraki ,  Shuji Nishi ,  Sachio Tsujino

发明人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiro Shiraki ,  Shuji Nishi ,  Sachio Tsujino

IPC分类号： G09G5/10

CPC分类号： G09G3/20 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2001/13606 ,  G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2330/021 ,  H01L27/124

摘要： The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal.In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.

摘要翻译： 本发明的目的在于提供一种能够降低采样电路的电路规模的单片驱动型显示装置，并且通过用外部提供的视频信号直接驱动源极驱动器来保持低功耗。 在具有用于显示视频的显示部分和用于驱动形成在同一绝缘基板上的显示部分的电路的单片驱动型显示装置中，与外部输入的多个位数据相关联地提供多个采样开关 数字视频信号。 采样开关基于采样信号进行开/关，从而针对每一位数据采样数字视频信号，并将信号转换为并行格式以输出到数据线。 输出的数字视频信号对数据线上的寄生电容进行充电并保持在其中。

公开(公告)号：US07333096B2

公开(公告)日：2008-02-19

申请号：US10316193

申请日：2002-12-11

申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2310/0213 ,  G09G2310/0232 ,  G09G2310/027 ,  G09G2310/0283 ,  G09G2310/0297 ,  G09G2310/04 ,  G09G2320/0214 ,  G09G2320/10 ,  G09G2330/021

摘要： A control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area is refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.

摘要翻译： 用于控制向像素PIX写入的控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于不显示的电压VB或电压VW ，不仅在第一帧中，而且在预定数量的帧中也是一次。 换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。 因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷， 可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时 限制功耗。

公开(公告)号：US07652652B2

公开(公告)日：2010-01-26

申请号：US10705775

申请日：2003-11-12

申请人： Kazuhiro Maeda ,  Sachio Tsujino ,  Hajime Washio ,  Yuhji Asoh

发明人： Kazuhiro Maeda ,  Sachio Tsujino ,  Hajime Washio ,  Yuhji Asoh

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G3/20 ,  G09G3/2011 ,  G09G2310/0297

摘要： The data signal line driving circuit of the present invention is arranged so that data signal line groups, each of which is made up of two data signal lines sequentially disposed, are connected to two video signal lines, each of which allows a two-phased video signal to be forwarded. A shift register SR, a drive switching circuit, and a waveform shaping circuit, that constitute a video signal fetching section, collect the data signal line groups via the two video signal lines as a single block. At this time, the data signal lines are respectively driven so as to fetch the video signal from the video signal lines into the data signal lines of the data signal line groups in each block. Thus, in performing multiphase development, it is possible to provide the data signal line driving circuit which can reduce power consumption in low resolution driving compared with a case of high resolution driving.

摘要翻译： 本发明的数据信号线驱动电路被布置成使得由两条数据信号线构成的数据信号线组连接到两条视频信号线，每条视频信号线允许两相视频 信号被转发。 构成视频信号取出部的移位寄存器SR，驱动切换电路以及波形整形电路通过两个视频信号线收集数据信号线组作为单个块。 此时，分别驱动数据信号线，以将视频信号从视频信号线提取到每个块中的数据信号线组的数据信号线中。 因此，在执行多相显影时，与高分辨率驱动的情况相比，可以提供能够降低分辨率驱动中的功耗的数据信号线驱动电路。

公开(公告)号：US07202846B2

公开(公告)日：2007-04-10

申请号：US10440077

申请日：2003-05-15

申请人： Kazuhiro Maeda ,  Sachio Tsujino ,  Keiji Takahashi ,  Hajime Washio

发明人： Kazuhiro Maeda ,  Sachio Tsujino ,  Keiji Takahashi ,  Hajime Washio

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0294 ,  G09G2330/021 ,  G09G2340/0421

摘要： A data signal line drive circuit is provided with: a shift register belonging to a system, whose stages correspond to respective sampling units for driving odd-number-th data signal lines; and a shift register belonging to another system, whose stages correspond to respective sampling units for driving even-number-th data signal lines. On the occasion of low-resolution mode, only either of the shift registers is operated, and in accordance with the outputs from the respective stages of the shift register which has been operated, timing signals, which are supplied to the sampling units corresponding to the stages of both shift registers, are generated. With this arrangement, even if one of input signals each having different signal line resolution is inputted, a signal line drive circuit which consumes a small amount of electric power can be realized, while it is possible to specify the timings of the operation of signal line drive sections for driving signal lines, in accordance with the input signal.

摘要翻译： 数据信号线驱动电路具有：属于系统的移位寄存器，其级对应于用于驱动奇数数据信号线的相应采样单元; 以及属于另一系统的移位寄存器，其级对应于用于驱动第二数据信号线的相应采样单元。 在低分辨率模式的情况下，仅移动寄存器中的任一个被操作，并且根据已经被操作的移位寄存器的各个级的输出，定时信号被提供给对应于 生成两个移位寄存器的阶段。 通过这样的配置，即使输入信号线分辨率不同的输入信号之一，也可以实现消耗少量电力的信号线驱动电路，同时可以规定信号线的动作时序 用于驱动信号线的驱动部分，根据输入信号。

公开(公告)号：US20080036753A1

公开(公告)日：2008-02-14

申请号：US11882533

申请日：2007-08-02

申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2310/0213 ,  G09G2310/0232 ,  G09G2310/027 ,  G09G2310/0283 ,  G09G2310/0297 ,  G09G2310/04 ,  G09G2320/0214 ,  G09G2320/10 ,  G09G2330/021

摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.

摘要翻译： 用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于非显示区域的电压VB或电压VW， 不仅在第一帧中显示，而且在预定数量的帧中显示一次。 换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。 因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷， 可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时 限制功耗。