Single loop frequency and phase detection
    31.
    发明授权
    Single loop frequency and phase detection 有权
    单回路频率和相位检测

    公开(公告)号:US08090064B2

    公开(公告)日:2012-01-03

    申请号:US12022725

    申请日:2008-01-30

    IPC分类号: H04L7/00

    CPC分类号: H04L7/0338

    摘要: In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.

    摘要翻译: 在一个实施例中,一种方法包括接收包括多个比特的数据信号。 该方法还包括产生时钟信号。 从数据信号以由时钟信号确定的采样率获取多个采样,并且确定在多个位中是否发生多个比特中的多个比特中的第一比特到第二比特的转换点 样品。 如果确定在多个样本内发生转换点,则包括多个状态的状态机从第一状态转变到第二状态。 如果第二状态指示时钟信号和数据信号之间的非零相位移量,则调整时钟信号以与数据信号相关。

    Digital Frequency Detector
    32.
    发明申请
    Digital Frequency Detector 审中-公开
    数字频率检测器

    公开(公告)号:US20100085086A1

    公开(公告)日:2010-04-08

    申请号:US12510211

    申请日:2009-07-27

    IPC分类号: H03B19/00

    摘要: In one embodiment, a method is described that includes receiving a first clock signal and a second clock signal; dividing the first clock signal by a value of n to generate a divided first clock signal; sampling the frequency detector the divided first clock signal with the second clock signal to generate a plurality of samples; generating a first adjustment signal if more than a predetermined number of consecutive samples in a set of consecutive samples have identical logical values; and generating a second adjustment signal if less than the predetermined number of consecutive samples in the set of consecutive samples have identical logical values.

    摘要翻译: 在一个实施例中,描述了一种包括接收第一时钟信号和第二时钟信号的方法; 将第一时钟信号除以n的值以产生分割的第一时钟信号; 对所述分频的第一时钟信号与所述第二时钟信号对所述频率检测器进行采样以产生多个采样; 如果一组连续样本中多于一个预定数量的连续样本具有相同的逻辑值,则产生第一调整信号; 以及如果小于所述连续样本集合中的预定数量的连续样本具有相同的逻辑值,则产生第二调整信号。

    System and apparatus for aperture time improvement
    33.
    发明授权
    System and apparatus for aperture time improvement 有权
    孔径时间改进的系统和装置

    公开(公告)号:US07629817B2

    公开(公告)日:2009-12-08

    申请号:US11960290

    申请日:2007-12-19

    IPC分类号: G01R19/00

    CPC分类号: H03K3/356139 H03K17/6871

    摘要: In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.

    摘要翻译: 在具体实施例中,一种装置包括在栅极处连接到第一输入信号电压的第一晶体管和在栅极处连接到第二输入信号电压的第二晶体管。 该装置还包括耦合到晶体管的去激活元件,去激活元件可操作以通过选择性地将去激活电流传输到第一晶体管的第一端子和第二晶体管的第二端子而使第一和第二晶体管去激活,从而提高电压 在第一和第二端子上达到足够大以使第一和第二晶体管去激活的值。 在特定实施例中,激活第一或第二晶体管传输来自装置的信号,并且去激活第一和第二晶体管防止信号从装置传输。

    System and Apparatus for Aperature Time Improvement
    34.
    发明申请
    System and Apparatus for Aperature Time Improvement 有权
    高温时间改进系统和装置

    公开(公告)号:US20080191770A1

    公开(公告)日:2008-08-14

    申请号:US11960290

    申请日:2007-12-19

    IPC分类号: H03K3/356 H03K17/687

    CPC分类号: H03K3/356139 H03K17/6871

    摘要: In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.

    摘要翻译: 在具体实施例中,一种装置包括在栅极处连接到第一输入信号电压的第一晶体管和在栅极处连接到第二输入信号电压的第二晶体管。 该装置还包括耦合到晶体管的去激活元件,去激活元件可操作以通过选择性地将去激活电流传输到第一晶体管的第一端子和第二晶体管的第二端子而使第一和第二晶体管去激活,从而提高电压 在第一和第二端子上达到足够大以使第一和第二晶体管去激活的值。 在特定实施例中,激活第一或第二晶体管传输来自装置的信号,并且去激活第一和第二晶体管防止信号从装置传输。

    Conditional pre-charge method and system

    公开(公告)号:US07027345B2

    公开(公告)日:2006-04-11

    申请号:US10043933

    申请日:2002-01-11

    IPC分类号: G11C7/00

    CPC分类号: G06F1/32

    摘要: Techniques, including a system and method, are disclosed for conditionally pre-charging a memory circuit, for example a flip-flop, and thus reducing power consumption. In an embodiment a method for reducing power consumption in a memory circuit, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. The method includes setting an input of the pre-charged stage to a first high logic level. Next, responsive to the setting of the input, the internal node is set to a low logic level within a first transparency window. Then responsive to the setting of the internal node, the evaluation stage changes the output of the evaluation stage to a second high logic level within the first transparency window. Lastly, when the input remains at the first high-logic level, the internal node is maintained at the low logic level through at least a second transparency window.

    Frequency synthesizer tuning
    36.
    发明授权
    Frequency synthesizer tuning 有权
    频率合成器调谐

    公开(公告)号:US08618840B1

    公开(公告)日:2013-12-31

    申请号:US13546702

    申请日:2012-07-11

    申请人: William W. Walker

    发明人: William W. Walker

    IPC分类号: H03B21/00

    摘要: A frequency synthesizer circuit includes a phase determinator configured to output a phase difference signal based on a phase difference between an output signal and a reference signal. The frequency synthesizer circuit may further include a voltage controlled oscillator configured, during a fine tuning mode, to generate the output signal based on the phase difference signal and a value of a frequency band signal. The voltage controlled oscillator may be further configured, during a coarse tuning mode, to generate the output signal based on a voltage and the value of the frequency band signal. The frequency synthesizer circuit may further include a control unit configured to generate the frequency band signal. The value of the frequency band signal may be static during the fine tuning mode and changing during the coarse tuning mode based on a frequency difference between the reference signal and the output signal.

    摘要翻译: 频率合成器电路包括:相位确定器,被配置为基于输出信号和参考信号之间的相位差来输出相位差信号。 频率合成器电路还可以包括在微调模式期间基于相位差信号和频带信号的值产生输出信号的压控振荡器。 压电振荡器还可以在粗调谐模式期间被配置为基于电压和频带信号的值产生输出信号。 频率合成器电路还可以包括被配置为产生频带信号的控制单元。 在微调模式期间,频带信号的值可以是静态的,并且基于参考信号和输出信号之间的频率差在粗调谐模式期间改变。

    Triple loop clock and data recovery (CDR)
    37.
    发明授权
    Triple loop clock and data recovery (CDR) 有权
    三回路时钟和数据恢复(CDR)

    公开(公告)号:US08300753B2

    公开(公告)日:2012-10-30

    申请号:US12510160

    申请日:2009-07-27

    IPC分类号: H04L7/00

    摘要: In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.

    摘要翻译: 在一个实施例中,一种方法包括访问具有参考时钟频率和参考时钟相位的参考时钟; 产生具有作为模拟控制电压设定和频率增益曲线的函数的输出时钟相位和输出时钟频率的输出时钟; 将模拟控制电压设置固定为预定电压; 在模拟控制电压设定下,在参考时钟频率的预定频率范围内选择一个频率增益曲线; 调整所述模拟控制电压设定以将所述输出时钟频率调整到所述参考时钟频率的另一预定频率范围内; 以及将输出时钟相位调整在输入数据流的输入数据相位的预定相位范围内。

    Symmetric Phase Detector
    38.
    发明申请
    Symmetric Phase Detector 审中-公开
    对称相位检测器

    公开(公告)号:US20120177162A1

    公开(公告)日:2012-07-12

    申请号:US13424728

    申请日:2012-03-20

    IPC分类号: H04L27/06 H03D13/00

    摘要: In one embodiment, a circuit includes a first mixer cell and a second mixer cell that each have respectively a first cell input, a second cell input, and a cell output. The circuit includes a first circuit input configured to receive a first input signal having a first phase. The first circuit input is connected to the first cell input of the first mixer cell and the second cell input of the second mixer cell. The circuit includes a second circuit input configured to receive a second input signal having a second phase separated from the first phase by a nominal value. The second circuit input is connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell.

    摘要翻译: 在一个实施例中,电路包括分别具有第一单元输入,第二单元输入和单元输出的第一混频器单元和第二混频器单元。 电路包括被配置为接收具有第一相位的第一输入信号的第一电路输入。 第一电路输入连接到第一混频器单元的第一单元输入和第二混频器单元的第二单元输入。 电路包括第二电路输入,其配置为接收具有与第一相分离的第二相位的标称值的第二输入信号。 第二电路输入连接到第一混频器单元的第二单元输入和第二混频器单元的第一单元输入。

    Clock and Data Recovery (CDR) Using Phase Interpolation
    39.
    发明申请
    Clock and Data Recovery (CDR) Using Phase Interpolation 有权
    时钟和数据恢复(CDR)使用相位插值

    公开(公告)号:US20100091927A1

    公开(公告)日:2010-04-15

    申请号:US12511365

    申请日:2009-07-29

    IPC分类号: H04L27/01

    摘要: In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.

    摘要翻译: 在一个实施例中,电路包括被配置为产生k个第一时钟信号的压控振荡器(VCO),每个第一时钟信号各自具有基于电荷泵控制电压信号的第一相位; 配置成接收k个第一时钟信号的一个或多个相位内插器(PI)和一个或多个第一反馈控制信号并产生m个第二时钟信号,每个第二时钟信号基于k个第一时钟信号和一个或多个第一反馈 控制信号; 第一相位检测器(PD),被配置为接收m个第二时钟信号,并且基于m个第二时钟信号产生一个或多个第一反馈控制信号; 配置为基于所述m个第二时钟信号产生一个或多个第二反馈控制信号的第二PD; 以及电荷泵,被配置为基于所述第二反馈控制信号输出所述电荷泵控制电压信号。

    Triple Loop Clock and Data Recovery (CDR)
    40.
    发明申请
    Triple Loop Clock and Data Recovery (CDR) 有权
    三回路时钟和数据恢复(CDR)

    公开(公告)号:US20100091925A1

    公开(公告)日:2010-04-15

    申请号:US12510160

    申请日:2009-07-27

    IPC分类号: H04L7/02

    摘要: In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.

    摘要翻译: 在一个实施例中,一种方法包括访问具有参考时钟频率和参考时钟相位的参考时钟; 产生具有作为模拟控制电压设定和频率增益曲线的函数的输出时钟相位和输出时钟频率的输出时钟; 将模拟控制电压设置固定为预定电压; 在模拟控制电压设定下,在参考时钟频率的预定频率范围内选择一个频率增益曲线; 调整所述模拟控制电压设定以将所述输出时钟频率调整到所述参考时钟频率的另一预定频率范围内; 以及将输出时钟相位调整在输入数据流的输入数据相位的预定相位范围内。