公开(公告)号：US20060271907A1

公开(公告)日：2006-11-30

申请号：US11429077

申请日：2006-05-08

申请人： Kyoko Izuha ,  Fumihiro Minami ,  Toshiaki Ueda ,  Ryuji Ogawa ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Fumihiro Minami ,  Toshiaki Ueda ,  Ryuji Ogawa ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031 ,  G06F17/5036

摘要： A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.

摘要翻译： 半导体电路图案设计方法包括以下操作。 通过将每个功能块中的多个单元放置为半导体电路的单元并在多个放置的单元之间执行布线来创建设计图案。 创建基于设计模式的掩模图案数据。 预测通过掩模图案数据在衬底上形成的预测图案。 检查通过掩模图案数据在衬底上形成的预测图案和目标图案之间的差值。 将差值与预定的允许变化量进行比较。 如果差异量大于比较中允许的变化量，则校正与用于预测预测图案的掩模图案数据相对应的设计图案中的单元的放置和布线中的至少一个。

公开(公告)号：US06985055B2

公开(公告)日：2006-01-10

申请号：US10403007

申请日：2003-04-01

申请人： Fumihiro Minami

发明人： Fumihiro Minami

IPC分类号： H01P3/08

CPC分类号： H01P3/003 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/088 ,  H01L2924/00

摘要： A transmission line, includes: a first input electrode located in a first level; a plurality of parallel stripe-shaped signal lines in the first level, one end of the signal lines connected to the first input electrode; a first output electrode connected to another end of the signal lines, facing to the first input electrode; a second input electrode adjacent to the first input electrode in a second level facing the first level; a plurality of stripe-shaped ground lines positioned alternately in between and at outer sides of each of the signal lines in the first level, one end of the ground lines connected to the second input electrode; and a second output electrode adjacent to the first output electrode in the second level and connected to another end of the ground lines.

摘要翻译： 传输线包括：位于第一电平的第一输入电极; 在所述第一级中的多条平行条形信号线，所述信号线的一端连接到所述第一输入电极; 连接到信号线的另一端的面向第一输入电极的第一输出电极; 邻近所述第一输入电极的面向所述第一电平的第二电平的第二输入电极; 多个条形接地线交替地位于第一电平的每个信号线的两侧和外侧之间，接地线的一端连接到第二输入电极; 以及与第二电平相邻的第一输出电极的第二输出电极，并连接到接地线的另一端。

公开(公告)号：US06714483B2

公开(公告)日：2004-03-30

申请号：US10358223

申请日：2003-02-05

申请人： Fumihiro Minami ,  Takashi Ohsawa ,  Yoshio Katayama

发明人： Fumihiro Minami ,  Takashi Ohsawa ,  Yoshio Katayama

IPC分类号： G01S1588

CPC分类号： G01S15/872 ,  B60W2550/142 ,  G01C9/00

摘要： An inclination angle measurement apparatus includes a first ultrasonic sensor (3) for sending an ultrasonic wave toward a road surface (2), second and third ultrasonic sensors (4 and 5) each for receiving an ultrasonic wave reflected from the road surface (2), and a calculation control circuit (14) for calculating an angle of inclination of a vehicle with respect to the road surface (2) based on a phase difference between ultrasonic waves received by the second and third ultrasonic sensors (4 and 5). Thus the inclination angle measurement apparatus can accurately measure the angle of inclination of the vehicle with respect to the road surface (2).

摘要翻译： 倾斜角测量装置包括用于向路面（2）发送超声波的第一超声波传感器（3）和用于接收从路面（2）反射的超声波的第二和第三超声波传感器（4和5） 以及用于基于由第二和第三超声波传感器（4和5）接收的超声波之间的相位差来计算车辆相对于路面（2）的倾斜角的计算控制电路（14）。 因此，倾斜角度测量装置可以精确地测量车辆相对于路面（2）的倾斜角度。

公开(公告)号：US06688917B2

公开(公告)日：2004-02-10

申请号：US10282216

申请日：2002-10-29

申请人： Hiroki Ushio ,  Fumihiro Minami

发明人： Hiroki Ushio ,  Fumihiro Minami

IPC分类号： H01R2500

CPC分类号： H01R27/02

摘要： An integral connector in which a power input connector and a power output connector are integrated with each other is disposed on a base plate.

摘要翻译： 电源输入连接器和电源输出连接器彼此集成的一体式连接器设置在基板上。

公开(公告)号：US06645842B2

公开(公告)日：2003-11-11

申请号：US10196928

申请日：2002-07-18

申请人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

发明人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

IPC分类号： H01L2144

CPC分类号： H01L23/5286 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0203 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost. The present invention forms an X-Y reference wiring grid using wirings of a total of M (M≧2) layers in which an n-th (n≧2) layer wiring intersects orthogonally with a (n−1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the (m+1)-th layer wiring and (m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of {square root over ( )}2 times of that of wiring in the reference wiring grid, and also wiring widths of {square root over ( )}2 times of that of wiring in the reference wiring layer.

摘要翻译： 公开了半导体集成电路器件，半导体集成电路布线方法和单元布置方法，其可以减少半导体集成电路的延迟并提高抗噪声性，实现布线设计，降低生产成本。本发明形式 使用总共M（M> = 2）层的布线的XY参考布线栅格，其中第n（n> = 2）层布线与第（n-1）层布线正交地相交，并形成 通过第（m + 1）层布线和（m + 2）层布线与每个正交相交的第（m + 2）层布线形成与参考布线层相交的具有45度或135度角的倾斜布线栅格 另外，斜交线栅格中的第（m + 1）层布线和第（m + 2）层布线具有{平方根以上的布线间距（参考布线栅中的布线的2倍） ，以及{平方根的布线宽度（参考中的布线的2倍） 连接布线层。

公开(公告)号：US06546540B1

公开(公告)日：2003-04-08

申请号：US09713050

申请日：2000-11-15

申请人： Mutsunori Igarashi ,  Masami Murakata ,  Takashi Mitsuhashi ,  Masaaki Yamada ,  Fumihiro Minami ,  Takashi Ishioka

发明人： Mutsunori Igarashi ,  Masami Murakata ,  Takashi Mitsuhashi ,  Masaaki Yamada ,  Fumihiro Minami ,  Takashi Ishioka

IPC分类号： G06F1750

CPC分类号： H01L23/528 ,  G06F1/10 ,  G06F17/5077 ,  H01L2924/0002 ,  H01L2924/00

摘要： With an automatic layout method, a first line having a firs line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.

摘要翻译： 利用自动布局方法，在规定的方向上产生具有第一线宽的第一线。 产生具有第二线宽并相对于第一线以倾斜角延伸的第二线，使得第二线终止于第一线的端部处，具有重叠区域。 根据重叠区域的形状，从数据库读出一个或多个VIA图案。 VIA图案被放置在重叠区域中，使得VIA图案之一位于第一和第二行的中心线的交叉处。 VIA模式是平行四边形的组合，包括正方形和矩形。

公开(公告)号：US06262487B1

公开(公告)日：2001-07-17

申请号：US09338593

申请日：1999-06-23

申请人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

发明人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

IPC分类号： H01L2348

CPC分类号： H01L23/5286 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0203 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility., achieve facility of wiring design, and reduce production cost. The present invention forms a X-Y reference wiring grid using wirings of a total of M (M≧2) layers in which an n-th (n≧2) layer wiring intersects orthogonally with a (n−1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the(m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring grid, and also wiring widths of {square root over (2)} times of that of wiring in the reference wiring layer.

摘要翻译： 公开了半导体集成电路器件，半导体集成电路布线方法和单元布置方法，其可以减少半导体集成电路的延迟并提高抗噪声性，实现布线设计的设计，并降低生产成本。本发明 使用其中n（n> = 2）层布线与第（n-1）层布线正交相交的总共M（M> = 2）层的布线形成XY参考布线栅格，并形成 通过与第（m + 1）层布线和第（m + 2）层布线正交地相交的第（m + 2）层布线，形成与参考布线层相交的具有45度或135度角的斜线布线， 使得斜线栅格中的第（m + 1）层布线和第（m + 2）层布线在布线中的布线间距大于（2）}倍的布线间距 参考线路，以及线路布线的{平方根超过（2）}倍的布线宽度 布线层。