公开(公告)号：US06813756B2

公开(公告)日：2004-11-02

申请号：US10279403

申请日：2002-10-24

申请人： Mutsunori Igarashi ,  Masami Murakata ,  Takashi Mitsuhashi ,  Masaaki Yamada ,  Fumihiro Minami ,  Takashi Ishioka

发明人： Mutsunori Igarashi ,  Masami Murakata ,  Takashi Mitsuhashi ,  Masaaki Yamada ,  Fumihiro Minami ,  Takashi Ishioka

IPC分类号： G06F1750

CPC分类号： H01L23/528 ,  G06F1/10 ,  G06F17/5077 ,  H01L2924/0002 ,  H01L2924/00

摘要： With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.

摘要翻译： 利用自动布局方法，在规定的方向上产生具有第一线宽的第一线。 产生具有第二线宽并相对于第一线以倾斜角延伸的第二线，使得第二线终止于第一线的端部处，具有重叠区域。 根据重叠区域的形状，从数据库读出一个或多个VIA图案。 VIA图案被放置在重叠区域中，使得VIA图案之一位于第一和第二行的中心线的交叉处。 VIA模式是平行四边形的组合，包括正方形和矩形。

公开(公告)号：US06546540B1

公开(公告)日：2003-04-08

申请号：US09713050

申请日：2000-11-15

申请人： Mutsunori Igarashi ,  Masami Murakata ,  Takashi Mitsuhashi ,  Masaaki Yamada ,  Fumihiro Minami ,  Takashi Ishioka

发明人： Mutsunori Igarashi ,  Masami Murakata ,  Takashi Mitsuhashi ,  Masaaki Yamada ,  Fumihiro Minami ,  Takashi Ishioka

IPC分类号： G06F1750

CPC分类号： H01L23/528 ,  G06F1/10 ,  G06F17/5077 ,  H01L2924/0002 ,  H01L2924/00

摘要： With an automatic layout method, a first line having a firs line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.

摘要翻译： 利用自动布局方法，在规定的方向上产生具有第一线宽的第一线。 产生具有第二线宽并相对于第一线以倾斜角延伸的第二线，使得第二线终止于第一线的端部处，具有重叠区域。 根据重叠区域的形状，从数据库读出一个或多个VIA图案。 VIA图案被放置在重叠区域中，使得VIA图案之一位于第一和第二行的中心线的交叉处。 VIA模式是平行四边形的组合，包括正方形和矩形。

公开(公告)号：US06436804B1

公开(公告)日：2002-08-20

申请号：US09810579

申请日：2001-03-19

申请人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

发明人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

IPC分类号： H01L2144

摘要： There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost. The present invention forms an X-Y reference wiring grid using wirings of a total of M (M≧2) layers in which an n-th (n≧2) layer wiring intersects orthogonally with a (n−1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the(m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring grid, and also wiring widths of {square root over (2)} times of that of wiring in the reference wiring layer.

公开(公告)号：US06645842B2

公开(公告)日：2003-11-11

申请号：US10196928

申请日：2002-07-18

申请人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

发明人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

IPC分类号： H01L2144

CPC分类号： H01L23/5286 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0203 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost. The present invention forms an X-Y reference wiring grid using wirings of a total of M (M≧2) layers in which an n-th (n≧2) layer wiring intersects orthogonally with a (n−1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the (m+1)-th layer wiring and (m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of {square root over ( )}2 times of that of wiring in the reference wiring grid, and also wiring widths of {square root over ( )}2 times of that of wiring in the reference wiring layer.

摘要翻译： 公开了半导体集成电路器件，半导体集成电路布线方法和单元布置方法，其可以减少半导体集成电路的延迟并提高抗噪声性，实现布线设计，降低生产成本。本发明形式 使用总共M（M> = 2）层的布线的XY参考布线栅格，其中第n（n> = 2）层布线与第（n-1）层布线正交地相交，并形成 通过第（m + 1）层布线和（m + 2）层布线与每个正交相交的第（m + 2）层布线形成与参考布线层相交的具有45度或135度角的倾斜布线栅格 另外，斜交线栅格中的第（m + 1）层布线和第（m + 2）层布线具有{平方根以上的布线间距（参考布线栅中的布线的2倍） ，以及{平方根的布线宽度（参考中的布线的2倍） 连接布线层。

公开(公告)号：US06262487B1

公开(公告)日：2001-07-17

申请号：US09338593

申请日：1999-06-23

申请人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

发明人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

IPC分类号： H01L2348

CPC分类号： H01L23/5286 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0203 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility., achieve facility of wiring design, and reduce production cost. The present invention forms a X-Y reference wiring grid using wirings of a total of M (M≧2) layers in which an n-th (n≧2) layer wiring intersects orthogonally with a (n−1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the(m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring grid, and also wiring widths of {square root over (2)} times of that of wiring in the reference wiring layer.

摘要翻译： 公开了半导体集成电路器件，半导体集成电路布线方法和单元布置方法，其可以减少半导体集成电路的延迟并提高抗噪声性，实现布线设计的设计，并降低生产成本。本发明 使用其中n（n> = 2）层布线与第（n-1）层布线正交相交的总共M（M> = 2）层的布线形成XY参考布线栅格，并形成 通过与第（m + 1）层布线和第（m + 2）层布线正交地相交的第（m + 2）层布线，形成与参考布线层相交的具有45度或135度角的斜线布线， 使得斜线栅格中的第（m + 1）层布线和第（m + 2）层布线在布线中的布线间距大于（2）}倍的布线间距 参考线路，以及线路布线的{平方根超过（2）}倍的布线宽度 布线层。

公开(公告)号：US07230554B2

公开(公告)日：2007-06-12

申请号：US11411143

申请日：2006-04-26

申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

IPC分类号： H03M1/00

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive. Moreover, a communication circuit for setting the number of data buses to be newly added to be less than two times a transmission on data, then encoding the data to be sent so as to make the numbers of “0” and “1” in the data to be sent through the data buses equal to each other and accordingly reducing the increase of the number of the data buses to a minimum and thereby suppressing the common phase power supply noise is provided. A communication apparatus comprising the communication circuit is also provided. Furthermore, the bypass capacitor C for noise suppression circuit is formed in an empty space in a ASIC. A polysilicon layer constituting one electrode of the bypass capacitor is formed in the substrate contact region formed between basic cells regularly arranged, each including a plurality of nMOS and pMOS transistors. This bypass capacitor C is connected between the high and the low level power supply lines to reduce the current running through the power supply line to suppress the EMI noise.

公开(公告)号：US07064691B2

公开(公告)日：2006-06-20

申请号：US10213065

申请日：2002-08-07

申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

IPC分类号： H03M7/20 ,  H04B1/38 ,  H04L5/16 ,  H04H7/00

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

摘要翻译： 噪声抑制电路包括内部电路，旁路电容器，第一和第二晶体管。 内部电路具有高低电平端子，低电平端子连接到低电平电源线。 内部电路提供使能和反相使能信号。 第一晶体管具有第一控制电极，一个主电极连接到高电平端子。 第一控制电极被提供有反相使能信号。 旁路电容器连接在第一晶体管的另一个主电极和低电平电源线之间。 第二晶体管连接在第一晶体管的另一个主电极和高电平电源线之间。 第二晶体管具有提供有使能信号的第二控制电极。 内部电路激活时，第二个晶体管不导通。

公开(公告)号：US06459331B1

公开(公告)日：2002-10-01

申请号：US09146035

申请日：1998-09-02

申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

IPC分类号： H03K500

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

摘要翻译： 噪声抑制电路包括内部电路，旁路电容器，第一和第二晶体管。 内部电路具有高低电平端子，低电平端子连接到低电平电源线。 内部电路提供使能和反相使能信号。 第一晶体管具有第一控制电极，一个主电极连接到高电平端子。 第一控制电极被提供有反相使能信号。 旁路电容器连接在第一晶体管的另一个主电极和低电平电源线之间。 第二晶体管连接在第一晶体管的另一个主电极和高电平电源线之间。 第二晶体管具有提供有使能信号的第二控制电极。 内部电路激活时，第二个晶体管不导通。

公开(公告)号：US20060197695A1

公开(公告)日：2006-09-07

申请号：US11411143

申请日：2006-04-26

申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

IPC分类号： H03M1/12

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive. Moreover, a communication circuit for setting the number of data buses to be newly added to be less than two times a transmission on data, then encoding the data to be sent 80 as to make the numbers of “0” and “1” in the data to be sent through the data buses equal to each other and accordingly reducing the increase of the number of the data buses to a minimum and thereby suppressing the common phase power supply noise is provided. A communication apparatus comprising the communication circuit is also provided. Furthermore, the bypass capacitor C for noise suppression circuit is formed in an empty space in a ASIC. A polysilicon layer constituting one electrode of the bypass capacitor is formed in the substrate contact region formed between basic cells regularly arranged, each including a plurality of nMOS and pMOS transistors. This bypass capacitor C is connected between the high and the low level power supply lines to reduce the current running through the power supply line to suppress the EMI noise.

公开(公告)号：US5801960A

公开(公告)日：1998-09-01

申请号：US963311

申请日：1997-11-03

申请人： Midori Takano ,  Fumihiro Minami ,  Mutsunori Igarashi

发明人： Midori Takano ,  Fumihiro Minami ,  Mutsunori Igarashi

IPC分类号： H01L21/82 ,  G06F17/50

CPC分类号： G06F17/5077

摘要： A layout method of designing a wiring pattern on a semiconductor integrated circuit chip according to the present invention comprises three steps of omitting a part of or all of a wiring pattern within cells for a plurality of circuit elements for layout results of these predetermined circuit elements to prepare wiring obstruction data (step 1); deciding a specific wiring path connecting between the cells with reference to the prepared wiring obstruction data (step 2); and repositioning of the cell to correct the layout with no design rule violation and no short between this specific wiring path and the wiring pattern within cells (step 3). The pattern layout is performed so that the specific wiring path is wired in the shortest length of wiring path without making a snaking wire path and also uncomplete wiring does not happen to occur.

摘要翻译： 根据本发明的在半导体集成电路芯片上设计布线图案的布置方法包括以下三个步骤：省略用于多个电路元件的单元内的布线图案的一部分或全部，用于将这些预定电路元件的布局结果 准备接线障碍物数据（步骤1）; 参照准备好的布线障碍物数据确定连接单元之间的具体布线路径（步骤2）; 并且重新定位单元以校正布局，而没有设计规则违反，并且在该特定布线路径和单元内的布线图案之间没有短路（步骤3）。 执行图案布局，使得特定布线路径布线在布线路径的最短长度中，而不会产生蛇线路，并且也不会发生不完全布线。