公开(公告)号：US20170047252A1

公开(公告)日：2017-02-16

申请号：US15175776

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract translation: 用于形成栅极结合的方法包括：在栅极结构上打开盖层和凹入栅极间隔物以暴露栅极导体; 在所述栅极间隔物上形成内部间隔物; 蚀刻与栅极结构的侧面相邻的接触开口，直到栅极结构下面的衬底; 以及在栅极结构的侧面上形成沟槽接触。 层间电介质（ILD）沉积在栅极导体上并且沟槽接触并在栅极结构上方。 ILD被打开以暴露栅极结构和栅极导体的一侧上的沟槽接触。 第二导电材料在一侧提供自对准接触，直到沟槽接触，并且形成到栅极导体的栅极接触，以及在栅极导体和自对准的有源区域之间的ILD内的水平连接 联系。

公开(公告)号：US09397049B1

公开(公告)日：2016-07-19

申请号：US14822654

申请日：2015-08-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/40 ,  H01L27/11 ,  H01L21/027

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract translation: 用于形成栅极结合的方法包括：在栅极结构上打开盖层和凹入栅极间隔物以暴露栅极导体; 在所述栅极间隔物上形成内部间隔物; 蚀刻与栅极结构的侧面相邻的接触开口，直到栅极结构下面的衬底; 以及在栅极结构的侧面上形成沟槽接触。 层间电介质（ILD）沉积在栅极导体上并且沟槽接触并在栅极结构上方。 ILD被打开以暴露栅极结构和栅极导体的一侧上的沟槽接触。 第二导电材料在一侧提供自对准接触，直到沟槽接触，并且形成到栅极导体的栅极接触，以及在栅极导体和自对准的有源区域之间的ILD内的水平连接 联系。

公开(公告)号：US09373697B2

公开(公告)日：2016-06-21

申请号：US14509392

申请日：2014-10-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sanjay C. Mehta ,  Shom S. Ponoth ,  Muthumanickam Sankarapandian ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785

Abstract: A method comprising steps of removing a first dielectric material, including a hard mask layer and one or more spacer material layers, from a semiconductor device having a sacrificial gate whose sidewalls being covered by said spacer material layers, and a raised source and a raised drain region with both, together with said sacrificial gate, being covered by said hard mask layer, wherein the removing is selective to the sacrificial gate, raised source region and raised drain region and creates a void between each of the raised source region, raised drain region and sacrificial gate. The method includes depositing a conformal layer of a second dielectric material to the semiconductor device, wherein the second material conforms in a uniform layer to the raised source region, raised drain region and sacrificial gate, and fills the void between each of the raised source region, raised drain region and sacrificial gate.