公开(公告)号：US11620243B2

公开(公告)日：2023-04-04

申请号：US17139750

申请日：2020-12-31

Applicant: Google LLC

Inventor： Vinod Chamarty ,  Xiaoyu Ma ,  Hongil Yoon ,  Keith Robert Pflederer ,  Weiping Liao ,  Benjamin Dodge ,  Albert Meixner ,  Allan Douglas Knies ,  Manu Gulati ,  Rahul Jagdish Thakur ,  Jason Rupert Redgrave

IPC: G06F13/16 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0877

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

公开(公告)号：US20220206796A1

公开(公告)日：2022-06-30

申请号：US17691615

申请日：2022-03-10

Applicant: Google LLC

Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

IPC: G06F9/30 ,  G06F7/57 ,  G06F9/38 ,  G06F15/80

Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

公开(公告)号：US11321802B2

公开(公告)日：2022-05-03

申请号：US16976316

申请日：2019-02-21

Applicant: GOOGLE LLC

Inventor： Albert Meixner ,  Dustin Michael DeWeese

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T1/60 ,  G06F8/41

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for supporting large lookup tables on an image processor. One of the methods includes receiving an input kernel program for an image processor having a two-dimensional array of execution lanes, a shift-register array, and a plurality of memory banks. If the kernel program has an instruction that reads a lookup table value for a lookup table partitioned across the plurality of memory banks, the instruction in the kernel program are replaced with a sequence of instructions that, when executed by an execution lane, causes the execution lane to read a first value from a local memory bank and a second value from the local memory bank on behalf of another execution lane belonging to a different group of execution lanes.

公开(公告)号：US11182138B2

公开(公告)日：2021-11-23

申请号：US16808007

申请日：2020-03-03

Applicant: Google LLC

Inventor： Albert Meixner

IPC: G06F8/41 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.

公开(公告)号：US10915773B2

公开(公告)日：2021-02-09

申请号：US15596286

申请日：2017-05-16

Applicant: Google LLC

Inventor： Edward Chang ,  Daniel Frederic Finchelstein ,  Szepo Robert Hung ,  Albert Meixner ,  Ofer Shacham

IPC: G06K9/00 ,  G06T1/20 ,  G11C19/00

Abstract: A method is described that includes loading an array of content into a two-dimensional shift register. The two-dimensional shift register is coupled to an execution lane array. The method includes repeatedly performing a first sequence including: shifting with the shift register first content residing along a particular row or column into another parallel row or column where second content resides and performing operations with a particular corresponding row or column of the execution lane array on the first and second content. The method also includes repeatedly performing a second sequence including: shifting with the shift register content from a set of first locations along a resultant row or column that is parallel with the rows or columns of the first sequence into a corresponding set of second locations along the resultant row or column. The resultant row or column has values determined from the operations of the first sequence.

公开(公告)号：US20210004232A1

公开(公告)日：2021-01-07

申请号：US17001097

申请日：2020-08-24

Applicant: Google LLC

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein ,  Qiuling Zhu

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30 ,  G06F15/80 ,  H04N3/14

Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

公开(公告)号：US10884959B2

公开(公告)日：2021-01-05

申请号：US16518503

申请日：2019-07-22

Applicant: Google LLC

Inventor： Vinod Chamarty ,  Xiaoyu Ma ,  Hongil Yoon ,  Keith Robert Pflederer ,  Weiping Liao ,  Benjamin Dodge ,  Albert Meixner ,  Allan Douglas Knies ,  Manu Gulati ,  Rahul Jagdish Thakur ,  Jason Rupert Redgrave

IPC: G06F13/16 ,  G06F12/0811 ,  G06F12/0877 ,  G06F12/0815

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

公开(公告)号：US10853908B2

公开(公告)日：2020-12-01

申请号：US16779257

申请日：2020-01-31

Applicant: Google LLC

Inventor： Albert Meixner

IPC: G06T1/60 ,  G06T1/20

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for supporting complex transfer functions on an image processor. One of the methods includes traversing, by each execution lane of an image processor using a shift-register array, a respective local support region and storing input pixels encountered during the traversal into local memory of the image processor. Each execution lane obtains from the local memory of the image processor one or more input pixels according to a complex transfer function. Each execution lane computes a respective output pixel for the kernel program using one or more input pixels obtained from the local memory according to the complex transfer function.

公开(公告)号：US10791284B2

公开(公告)日：2020-09-29

申请号：US16659702

申请日：2019-10-22

Applicant: Google LLC

Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

IPC: G09G5/36 ,  H04N5/262 ,  G06T1/60 ,  G06T1/20

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

公开(公告)号：US10685423B2

公开(公告)日：2020-06-16

申请号：US16585834

申请日：2019-09-27

Applicant: Google LLC

Inventor： Hyunchul Park ,  Albert Meixner ,  Qiuling Zhu ,  William Mark

IPC: G06T1/60 ,  G06T1/20 ,  G09G5/36 ,  G06F3/06 ,  G06F9/50 ,  G06F30/20 ,  G06F30/33 ,  G06F12/084 ,  G06F12/0842 ,  G06F117/08

Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.