公开(公告)号：US6094667A

公开(公告)日：2000-07-25

申请号：US3507

申请日：1998-01-06

申请人： Xuping Zhou ,  Changming Zhou ,  Guoliang Shou

发明人： Xuping Zhou ,  Changming Zhou ,  Guoliang Shou

IPC分类号： H03H21/00 ,  H03H17/00 ,  H04B1/10 ,  H04L25/03 ,  G06F17/10 ,  H04L27/00

CPC分类号： H03H17/00 ,  H04L25/03834

摘要： In a method is disclosed for transmitting and receiving a transmission data signal, after the transmission data signal is generated, it is modulated by a first time spread root Nyquist filter to generate a transmission signal. The signal is then transmitted and received, whereupon the signal is transformed into a baseband signal. The baseband signal is then demodulated through a second time spread root Nyquist filter to revive the transmission data signal. An apparatus is also disclosed that performs this method. In addition, methods of separately transmitting and receiving signals are also described.

摘要翻译： 公开了一种用于发送和接收发送数据信号的方法，在发送数据信号产生之后，由第一时间扩展根奈奎斯特滤波器对其进行调制以产生发送信号。 然后发送和接收信号，由此将信号变换成基带信号。 然后通过第二时间扩展根奈奎斯特滤波器对基带信号进行解调，以恢复发送数据信号。 还公开了执行该方法的装置。 此外，还描述了单独发送和接收信号的方法。

公开(公告)号：US6084922A

公开(公告)日：2000-07-04

申请号：US61097

申请日：1998-04-16

申请人： Changming Zhou ,  Xuping Zhou ,  Guoliang Shou

发明人： Changming Zhou ,  Xuping Zhou ,  Guoliang Shou

IPC分类号： H04B1/26 ,  H04B1/16 ,  H04B7/26 ,  H04J1/00 ,  H04M1/73 ,  H04W52/02 ,  H04L27/06

CPC分类号： H04B1/1615 ,  H04W52/029

摘要： A waiting circuit which is utilized in a mobile communication system. The waiting circuit detects a predetermined signal from a base station. The waiting circuit starts other circuits in the mobile communication system which are in a sleep mode when the predetermined signal is received. The predetermined signal is generated in the base station. The predetermined signal has a speed equal to a predetermined symbol rate and is modulated to be an intermediate frequency signal. The intermediate frequency signal is sampled in response to a sampling clock that has a speed equal to an integer times the symbol rate. The sampled intermediate frequency signal is input to a match filter which multiplies the sample signal by a predetermined sequence of coefficients.

摘要翻译： 一种在移动通信系统中使用的等待电路。 等待电路检测来自基站的预定信号。 当接收到预定信号时，等待电路开始处于睡眠模式的移动通信系统中的其他电路。 在基站中产生预定信号。 预定信号具有等于预定符号速率的速度并被调制成中频信号。 响应于具有等于符号率的整数倍的速度的采样时钟对中频信号进行采样。 采样的中频信号被输入到将采样信号乘以预定系数序列的匹配滤波器。

公开(公告)号：US5945875A

公开(公告)日：1999-08-31

申请号：US47457

申请日：1998-03-25

申请人： Xuping Zhou ,  Guoliang Shou ,  Changming Zhou

发明人： Xuping Zhou ,  Guoliang Shou ,  Changming Zhou

IPC分类号： H04L27/22 ,  H04L27/233 ,  H03D3/00

CPC分类号： H04L27/2331

摘要： A .pi./n shift PSK demodulator of this invention is formed with a digital logical means through the following method. XOR4 calculates the ex-OR operation between the present sample through .pi./4 shift QPSK output from SH2 and the previous one output from SH1. Accumulating 1 among the outputs from XOR4 in the first operation means 5 and multiplying it by .pi./8 obtains the absolute phase difference between the present and the previous symbols. The former or latter four bits from SH1 are subtracted from the corresponding former or latter four bits from SH2, and the result of each bit is summed and its sign is added to the absolute phase data in sign addition means 10. After the phase offset is subtracted from the outputs from 10, it is demodulated into the original one in judgment circuit 13.

摘要翻译： 本发明的π/ n移位PSK解调器通过以下方法由数字逻辑装置形成。 XOR4通过从SH2输出的pi / 4移位QPSK和SH1的前一个输出来计算当前采样之间的异或运算。 在第一操作装置5中从XOR4的输出中累积1，并将其乘以pi / 8获得当前和先前符号之间的绝对相位差。 来自SH1的前者或后者的四位从SH2的相应的前一个或后四位中减去，每个位的结果被相加，并且其符号被加到符号加法装置10中的绝对相位数据。在相位偏移为 从10的输出中减去，在判断电路13中被解调成原来的。

公开(公告)号：US06064690A

公开(公告)日：2000-05-16

申请号：US75861

申请日：1998-05-12

申请人： Changming Zhou ,  Xuping Zhou ,  Guolinag Shou

发明人： Changming Zhou ,  Xuping Zhou ,  Guolinag Shou

IPC分类号： H04B1/707 ,  H04B1/69

CPC分类号： H04B1/707 ,  H04B1/7093

摘要： A spread spectrum communication system wherein spreading codes for in-phase and quadrature components are composed by addition and subtraction and the received signal is multiplied by these composed codes for despreading. The communication system comprises a transmitter generating in-phase and quadrature components. The transmitter includes a spreading circuit for spreading the in-phase and quadrature components. The system further includes a receiver, a phase correction circuit for correcting the phase of despreaded components, a rake combiner for combining the components corrected by the phase correction circuit and a circuit for outputting a combined signal and a delay detection circuit for delaying detection of the combined signal. The receiver also comprises a provisional judgment portion for judging the phase of a pair of the in-phase and quadrature phase components. The phase correction circuit corrects the phase according to the phase judged by the provisional judgment portion.

摘要翻译： 扩展频谱通信系统，其中用于同相和正交分量的扩展码由加法和减法组成，并且接收的信号乘以这些组合代码用于解扩。 通信系统包括产生同相和正交分量的发射机。 发射机包括用于扩展同相和正交分量的扩展电路。 该系统还包括接收机，用于校正解扩部件的相位的相位校正电路，用于组合由相位校正电路校正的分量的组合器和用于输出组合信号的电路和延迟检测电路的延迟检测电路 组合信号。 接收机还包括用于判断一对同相和正交相位分量的相位的临时判断部分。 相位校正电路根据由临时判断部判定的相位来校正相位。

公开(公告)号：US6073149A

公开(公告)日：2000-06-06

申请号：US60000

申请日：1998-04-15

申请人： Guoliang Shou ,  Kazunori Motohashi ,  Ying Chen ,  Takashi Tomatsu ,  Changming Zhou ,  Jie Chen

发明人： Guoliang Shou ,  Kazunori Motohashi ,  Ying Chen ,  Takashi Tomatsu ,  Changming Zhou ,  Jie Chen

IPC分类号： G06F7/49 ,  G06J1/00 ,  G06F7/00 ,  G06G7/00

CPC分类号： G06F7/49 ,  G06F2207/386

摘要： A computational circuit for a multi-value addition comprising a parallel adder, an output adder, a quantizing portion and a logic conversion portion. Addition circuits in the above adders and thresholding circuits in the above quantizing portion consist of voltage-driven circuits including capacitive couplings.

摘要翻译： 一种用于多值附加的计算电路，包括并行加法器，输出加法器，量化部分和逻辑转换部分。 上述量化部分中的上述加法器和阈值电路中的加法电路由包括电容耦合的电压驱动电路组成。

公开(公告)号：US5956333A

公开(公告)日：1999-09-21

申请号：US781631

申请日：1997-01-10

申请人： Changming Zhou ,  Guoliang Shou ,  Kenzo Urabe ,  Tetsuhiko Miyatani

发明人： Changming Zhou ,  Guoliang Shou ,  Kenzo Urabe ,  Tetsuhiko Miyatani

IPC分类号： H03H17/00 ,  H04B1/7107 ,  H04J13/00 ,  H04K1/00

CPC分类号： H04B1/71075

摘要： A multi-user demodulator eliminates synchronization problems without interference cancellation. A threshold process is applied to a despread signal to extract each user's signal. The extracted signals are respread, and those respread signals other than a specifier user's signal are subtracted from the received signal to ideally extract the specific user's signal.

摘要翻译： 多用户解调器消除了无干扰消除的同步问题。 对解扩信号应用阈值处理以提取每个用户的信号。 提取的信号被重新发送，并且从接收到的信号中减去除指定者用户信号之外的那些再现信号，以理想地提取特定用户的信号。

公开(公告)号：US5930157A

公开(公告)日：1999-07-27

申请号：US895272

申请日：1997-07-16

申请人： Ichiro Matsumoto ,  Changming Zhou ,  Guoliang Shou

发明人： Ichiro Matsumoto ,  Changming Zhou ,  Guoliang Shou

IPC分类号： G06F17/10 ,  G06F17/15 ,  G06J1/00 ,  G06F7/12

CPC分类号： G06J1/00

摘要： The autocorrelation coefficient operator 60 carries out an integration operation to determine the autocorrelation coefficient for audio signal processing or other types of signal processing at high speed with low power consumption. The input signal S is digitized in the A/D converter 30 to the digital signal SP and supplied to a delay unit 40, which delays and holds the digital signal SP sequentially. A sample holder 45 also samples and holds the analog signal S in synchronization with the delay unit 40. When the number of sampled values held by the sample holder 45 reaches a predetermined value, the sample holder 45 outputs the sampled values at the same time in accordance with a sampling clock signal CK which is supplied by a clock signal generator 35. Delayed values held in the delay unit 40 are shifted and output sequentially in accordance with a shift clock signal SCK, the frequency of which is higher than that of the sampling clock signal CK. A weighted addition circuit 50 integrates these sampled values and the delayed values to calculate the autocorrelation coefficient R.

摘要翻译： 自相关系数运算器60执行积分运算，以低功耗确定音频信号处理的自相关系数或其他类型的信号处理。 输入信号S在A / D转换器30中数字化为数字信号SP，并提供给延迟单元40，延迟单元40依次延迟和保持数字信号SP。 样本保持器45还与延迟单元40同步地采样并保持模拟信号S.当采样保持器45保持的采样值的数量达到预定值时，样本保持器45同时输出采样值 根据由时钟信号发生器35提供的采样时钟信号CK。保持在延迟单元40中的延迟值根据频率高于采样的移位时钟信号SCK被顺序移位和输出 时钟信号CK。 加权加法电路50对这些采样值和延迟值进行积分，以计算自相关系数R.

公开(公告)号：US06512785B1

公开(公告)日：2003-01-28

申请号：US09247828

申请日：1999-02-11

申请人： Changming Zhou ,  Xuping Zhou ,  Kunihiko Suzuki ,  Xiaoxing Zhang ,  Takashi Tomatsu

发明人： Changming Zhou ,  Xuping Zhou ,  Kunihiko Suzuki ,  Xiaoxing Zhang ,  Takashi Tomatsu

IPC分类号： H04B1707

CPC分类号： H04B1/7093 ,  H04B2201/70707

摘要： A matched filter bank including a plurality of matched filters and a sampling and holding units commonly used by the total matched filters. Therefore, the circuit size is diminished. An inverting amplifier for the matched filter with a variable gain includes an input capacitance, an inverting amplifier connected to an output of the input capacitance, and a plurality of feedback capacitances connected between an input and output of the inverting amplifier. A plurality of switches are connected to input side of the feedback capacitances for alternatively connecting the feedback capcitanec to the input of the inverting amplifier or a reference voltage. The feedback capacitances connected to the reference voltage are invalid with respect to a composite capacitance of the feedback capacitance and have no influence to the amplifier.

摘要翻译： 包括多个匹配滤波器的匹配滤波器组和由总匹配滤波器通常使用的采样和保持单元。 具有可变增益的匹配滤波器的反相放大器包括输入电容，连接到输入电容的输出的反相放大器和连接在输入电容的输入和输出之间的多个反馈电容 反相放大器。 多个开关连接到反馈电容的输入侧，用于将反馈capcitanec交替地连接到反相放大器的输入端或参考电压。 连接到参考电压的反馈电容相对于反馈电容的复合电容无效，并且对放大器没有影响。

公开(公告)号：US06563373B1

公开(公告)日：2003-05-13

申请号：US09165301

申请日：1998-10-02

申请人： Guoliang Shou ,  Kunihiko Suzuki ,  Changming Zhou

发明人： Guoliang Shou ,  Kunihiko Suzuki ,  Changming Zhou

IPC分类号： H03H1502

CPC分类号： H04B1/7093 ,  H03H11/04

摘要： An analog calculation circuit in a filter circuit is corrected in the calculation error by estimating the error from a calculation result of known inputs and known multiplier. A multiplier is changed according to the estimated error. The filter circuit has a voltage to current converter at an input side and a current to voltage converter at an output side and a calculation of current is performed therein.

摘要翻译： 滤波器电路中的模拟计算电路通过从已知输入和已知乘数的计算结果估计误差来校正计算误差。 根据估计的误差改变乘数。 滤波电路在输入侧具有电压 - 电流转换器，在输出侧具有电流 - 电压转换器，并且在其中执行电流计算。

公开(公告)号：US5959875A

公开(公告)日：1999-09-28

申请号：US812650

申请日：1997-03-07

申请人： Nobuaki Kawahara ,  Kenzo Urabe ,  Changming Zhou ,  Guoliang Shou

发明人： Nobuaki Kawahara ,  Kenzo Urabe ,  Changming Zhou ,  Guoliang Shou

IPC分类号： G06G7/19

CPC分类号： G06G7/1921

摘要： A signal characterizer for performing functional transformations such as Fast Fourier Transforms (FFTs), which converts an input serial analog signal into a plurality of parallel discrete signals using an analog-type serial-to-parallel converter. The discrete signals are then supplied to the input terminals of butterfly operation circuits to process the parallel discrete signals into a plurality of transformed signals. A switch supplies the transformed signals to a serial signal output terminal. The switch is controlled by a controller so that the input signal sequence is converted to a serial signal sequence according to a predetermined order.

摘要翻译： 一种用于执行诸如快速傅立叶变换（FFT）的功能变换的信号表征器，其使用模拟型串并转换器将输入的串行模拟信号转换为多个并行离散信号。 然后将离散信号提供给蝶形运算电路的输入端，以将并行离散信号处理成多个变换信号。 开关将变换的信号提供给串行信号输出端子。 开关由控制器控制，使得输入信号序列根据预定顺序被转换成串行信号序列。