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    Complex multiplication circuit
    2.
    发明授权
    Complex multiplication circuit 失效
    复数乘法电路

    公开(公告)号：US6122654A

    公开(公告)日：2000-09-19

    申请号：US66540

    申请日：1998-04-27

    Applicant: Changming Zhou ,  Xuping Zhou ,  Guoliang Shou

    Inventor： Changming Zhou ,  Xuping Zhou ,  Guoliang Shou

    IPC: G06F17/10 ,  G06F17/16 ,  G06G7/22 ,  H03F1/34 ,  H03H15/00 ,  H03H17/02 ,  G06F7/52

    CPC classification number: G06G7/22

    Abstract: A complex multiplication circuit of a calculation formula equivalent but different from the usual formula.The calculation formula is as follows:Pr={x(a+b)-b(x+y)} equivalent to (ax-by)Pi={y(a-b)+b(x+y)} equivalent to (ay+bx)Here,Input signal: x+jyMultiplier:a+jbMultiplication result:Pr+jPi.

    Abstract translation: 计算公式的复乘法电路等效但不同于通常的公式。 计算公式如下：等价于（ay）的（ax-by）Pi = {y（ab）+ b（x + y）}的Pr = {x（a + b）-b（x + y） + bx）这里，输入信号：x + jy乘数：a + jb乘法结果：Pr + jPi。

    Receiver for code division multiple access communication system
    4.
    发明授权
    Receiver for code division multiple access communication system 失效
    接收机用于码分多址通信系统

    公开(公告)号：US5974038A

    公开(公告)日：1999-10-26

    申请号：US864784

    申请日：1997-05-29

    Applicant: Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori

    Inventor： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori

    IPC: H04B1/707 ,  H04B1/7075 ,  H04B1/7093 ,  H04B1/7115 ,  H04L7/00 ,  H04B7/216

    CPC classification number: H04B1/708 ,  H04B1/7093 ,  H04B1/7115 ,  H04B2201/70709

    Abstract: This invention reduces electric power consumption of a CDMA communication system receiver while it is in the wait mode. A received spread spectrum signal is demodulated in multiplication means into baseband signals Ri and Rq, and inputted into a complex matched filter. This filter is intermittently driven by supply voltage control means to perform acquisition of received signals. When an electric power calculation circuit detects the output of the filter to reach a peak equal to or greater than a predetermined value, the received signals undergo acquisition by controlling n number of correlators 26-1 to 26-n to work by a correlator controlling circuit. Moreover, de-spreading is performed. The outputs from each correlator 46-1 to 26-n are given to a RAKE combiner and demodulated by the RAKE by a combining and demodulating circuit.

    Abstract translation: 本发明在CDMA通信系统接收机处于等待模式时降低电力消耗。 接收的扩频信号在乘法装置中被解调为基带信号Ri和Rq，并输入到复匹配滤波器中。 该滤波器由电源电压控制装置间歇地驱动，以执行接收信号的采集。 当电力计算电路检测到滤波器的输出达到等于或大于预定值的峰值时，通过控制n个相关器26-1至26-n来由相关器控制电路工作来接收接收的信号 。 此外，进行解扩。 来自每个相关器46-1至26-n的输出被提供给RAKE组合器，并由RAKE通过组合和解调电路进行解调。

    Spread spectrum communications system for high-speed communications
    5.
    发明授权
    Spread spectrum communications system for high-speed communications 失效
    扩频通信系统，用于高速通信

    公开(公告)号：US5930290A

    公开(公告)日：1999-07-27

    申请号：US841217

    申请日：1997-04-30

    Applicant: Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Kenzo Urabe

    Inventor： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Kenzo Urabe

    IPC: H04B1/707 ,  H04B1/7093 ,  H04J13/10 ,  H04B15/00 ,  H04B7/216

    CPC classification number: H04J13/0077 ,  H04B1/7093

    Abstract: A fast spread spectrum communication system is provided, having fewer circuits and requiring fewer PN codes to be assigned to a user. A series of digital data to be transmitted, is divided into 4-bit frames. The 4-bit data of each frame is divided into the first through fourth elements in a predetermined order. The first complex number is constructed by the first and second elements, and the second complex number is determined according to the value of the third and fourth elements. The spectrum of the data to be transmitted is spread by multiplying these complex numbers. Four matched filters despread a received signal by different combinations of PN codes stored in a receiver. The first through fourth elements are recovered according to the outputs of the matched filters.

    Abstract translation: 提供了一种快速扩频通信系统，具有较少的电路并且需要较少的PN码来分配给用户。 要发送的一系列数字数据被分为4位帧。 每帧的4位数据按预定顺序分成第一至第四元素。 第一复数由第一和第二元素构成，第二复数根据第三和第四元素的值确定。 要传输的数据的频谱通过乘以这些复数来传播。 四个匹配滤波器通过存储在接收机中的PN码的不同组合对接收信号进行解扩。 根据匹配滤波器的输出，恢复第一至第四元件。

    Matched filter circuit
    6.
    发明授权
    Matched filter circuit 失效
    匹配滤波电路

    公开(公告)号：US5872466A

    公开(公告)日：1999-02-16

    申请号：US686950

    申请日：1996-07-26

    Applicant: Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

    Inventor： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

    IPC: H03H11/04 ,  H03H17/02 ,  H04B1/707 ,  H04B1/7093 ,  H04L7/00 ,  H04L7/10 ,  H03K5/00

    CPC classification number: H03H11/04 ,  H03H17/0254

    Abstract: A matched filter with reduced electric power consumption is disclosed. The matched filter circuit power consumption is reduced by stopping the electric power supply to an unnecessary circuit since input signal is partially sampled just after an acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups "1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.

    Abstract translation: 公开了具有降低的电力消耗的匹配滤波器。 由于输入信号在采集之后被部分采样，因此通过停止对不必要的电路的电力来降低匹配滤波器电路的功耗。 由于扩展码是1位数据串，采样和保持的输入信号通过多路复用器分支到信号组“1”和“-1”。 各组中的信号通过电容耦合并联并且在电路中间歇地供电。

    Inverted amplifying circuit
    7.
    发明授权
    Inverted amplifying circuit 失效
    反相放大电路

    公开(公告)号：US5783961A

    公开(公告)日：1998-07-21

    申请号：US764637

    申请日：1996-12-11

    Applicant: Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

    Inventor： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

    IPC: H03K19/0948 ,  H03F1/02 ,  H03F1/34 ,  H03F3/46 ,  H03F3/72 ,  H03K5/153 ,  H03H11/26

    CPC classification number: H03F3/72

    Abstract: The present invention has an object to provide an inverted amplifying circuit with improved accuracy of output and reduced electric power consumption. In an inverted amplifying circuit according to the present invention, a MOS switch is connected between pMOS and nMOS of a CMOS inverter and between balancing resistances. The MOS switch is opened when the inverted amplifying circuit does not work.

    Abstract translation: 本发明的目的是提供一种具有提高的输出精度和降低的电力消耗的反相放大电路。 在根据本发明的反相放大电路中，MOS开关连接在CMOS反相器的pMOS和nMOS之间以及平衡电阻之间。 当反相放大电路不工作时，MOS开关打开。

    Matched filter circuit
    8.
    发明授权
    Matched filter circuit 有权
    匹配滤波电路

    公开(公告)号：US06625205B1

    公开(公告)日：2003-09-23

    申请号：US09332198

    申请日：1999-06-14

    Applicant: Changming Zhou ,  Kunihiko Suzuki

    Inventor： Changming Zhou ,  Kunihiko Suzuki

    IPC: H04L2706

    CPC classification number: H04B1/7093 ,  H04B1/708 ,  H04B2201/7071

    Abstract: A matched filter having a set of registers to successively store a digital voltage. The matched filter includes a cumulative shift register, a number of exclusive-or circuits, and an analog adder. The cumulative shift register has a number of stages in which each stage has one bit corresponding to the shift register. The exclusive-or circuits each perform an exclusive-or function on each bit of the digital data and the one bit coefficient while the analog adder sums outputs from the exclusive-or circuits.

    Abstract translation: 具有一组寄存器以连续存储数字电压的匹配滤波器。 匹配滤波器包括累积移位寄存器，多个异或电路和模拟加法器。 累积移位寄存器具有多个阶段，其中每个级具有对应于移位寄存器的一位。 在模拟加法器对来自异或电路的输出进行求和时，异或电路各自对数字数据的每一位和一位系数进行排他或功能。

    Analog to digital converter
    9.
    发明授权
    Analog to digital converter 失效
    模数转换器

    公开(公告)号：US06340942B1

    公开(公告)日：2002-01-22

    申请号：US09413475

    申请日：1999-10-06

    Applicant: Changming Zhou ,  Kunihiko Suzuki ,  Takashi Tomatsu ,  Masataka Fukui

    Inventor： Changming Zhou ,  Kunihiko Suzuki ,  Takashi Tomatsu ,  Masataka Fukui

    IPC: H03M134

    CPC classification number: H03M1/42

    Abstract: An analog to digital converter comprises a differential input portion that receives an input voltage and a reference voltage and has a first and second output terminals, a positive feedback portion connected to said first and second output terminals, a buffer if CMOSFETs connected at its input to the first output terminal, a second buffer connected at its input to the second output terminal, and a comparison circuit including a first switching portion connected between the first and second output terminals for connecting and disconnecting the first and second output terminals in response to a comparison clock signal. The comparison circuit is connected at its output to the first or second buffer. The input voltage and the reference voltage are compared when said switching portion changes from the connecting condition to the disconnecting condition in response to the comparison clock signal.

    Abstract translation: 模数转换器包括差分输入部分，其接收输入电压和参考电压，并且具有第一和第二输出端子，连接到所述第一和第二输出端子的正反馈部分，如果CMOSFET在其输入端连接到 第一输出端子，在其输入端连接到第二输出端子的第二缓冲器，以及比较电路，包括连接在第一和第二输出端子之间的第一开关部分，用于响应于比较来连接和断开第一和第二输出端子 时钟信号。 比较电路在其输出端连接到第一或第二缓冲器。 当所述切换部分响应于比较时钟信号而从连接状态变为断开状态时，比较输入电压和参考电压。

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