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    LOGIC CIRCUITRY PACKAGE
    33.
    发明申请
    LOGIC CIRCUITRY PACKAGE 有权

    公开(公告)号：US20210372840A1

    公开(公告)日：2021-12-02

    申请号：US16768650

    申请日：2019-10-25

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Michael W. CUMBIE ,  James Michael GARDNER ,  Scott A. LINN

    IPC: G01F23/24 ,  G01F23/00 ,  B41J2/175

    Abstract: A logic circuitry package includes an interface to communicate with a print apparatus logic circuit and at least one logic circuit including at least one heater and a temperature sensor. The at least one logic circuit is configured to receive, via the interface, a heater command to address the at least one heater. The at least one logic circuit is configured to receive, via the interface, subsequent to the heater command, a sensor command corresponding to a sensor ID to address the temperature sensor. The at least one logic circuit is configured to transmit, via the interface, a digital value in response to the sensor command. The digital value corresponds to a print material level of a print material within a reservoir.

    LOGIC CIRCUITRY
    34.
    发明申请
    LOGIC CIRCUITRY 有权

    公开(公告)号：US20210326297A1

    公开(公告)日：2021-10-21

    申请号：US17364052

    申请日：2021-06-30

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Stephen D. PANSHIN ,  Scott A. LINN

    IPC: G06F13/42 ,  B41J2/175 ,  G03G21/18 ,  G06F13/38 ,  H04N1/00

    Abstract: Replaceable print material supply cartridges for printers are disclosed herein. An example replaceable print material supply cartridge includes logic circuitry that is to determine a position of the replaceable print material supply cartridge by initiating a first voltage on a data contact during a time period, monitoring a timer without reference to a clock signal at a clock contact from a serial data bus, and maintaining a first voltage on the data contact for a duration of time. After expiration of the duration, the logic circuitry is to cause the data contact to assume a second voltage, different than the first voltage, and the logic circuitry is to read data from the memory and cause transmission of a data signal via the serial data bus interface.

    IDENTIFYING RANDOM BITS IN CONTROL DATA PACKETS
    36.
    发明申请
    IDENTIFYING RANDOM BITS IN CONTROL DATA PACKETS 有权

    公开(公告)号：US20210229430A1

    公开(公告)日：2021-07-29

    申请号：US16769396

    申请日：2019-02-06

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： John ROSSI ,  Scott A. LINN ,  James Michael GARDNER ,  Erik D. NESS

    IPC: B41J2/045

    Abstract: A fluid ejection controller interface includes input logic to receive control data packets and a first clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the input logic identifies the random bits in the received control data packets to facilitate the creation of modified control data packets. The fluid ejection controller interface includes a clock signal generator to generate a second clock signal that is different than the first clock signal, and output logic to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the second clock signal.

    LOGIC CIRCUITRY PACKAGE
    37.
    发明申请
    LOGIC CIRCUITRY PACKAGE 有权

    公开(公告)号：US20210224219A1

    公开(公告)日：2021-07-22

    申请号：US16767584

    申请日：2019-10-25

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Scott A. LINN

    IPC: G06F13/42 ,  B41J2/175 ,  G01F23/00 ,  G06F1/12

    Abstract: A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit and at least one logic circuit. The at least one logic circuit is configured to receive, via the interface, a request to replace an internal clock signal from an internal clock generator of the logic circuitry package with an external test clock signal. The at least one logic circuit is configured to receive, via the interface, the external test clock signal. The at least one logic circuit is configured to replace the internal clock signal with the external test clock signal in the logic circuitry package.

    LOGIC CIRCUITRY
    38.
    发明申请
    LOGIC CIRCUITRY 有权

    公开(公告)号：US20210221125A1

    公开(公告)日：2021-07-22

    申请号：US16771092

    申请日：2018-12-03

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Stephen D. PANSHIN ,  Jefferson P. WARD ,  Scott A. LINN ,  James Michael GARDNER

    IPC: B41J2/045

    Abstract: In an example, a logic circuitry package is configured to be addressable via a first address and at least one second address and comprises a first logic circuit. The first address may be an address for the first logic circuit, and the package may be configured such that, in response to a first command indicative of a first command time period sent to the first address, the package is accessible via at least one second address for a duration of the first command time period; and in response to a second command indicative of a second command time period sent to the first address, the first logic circuit is to, for a duration of the second command time period, disregard traffic sent to the first address.

    PRINT COMPONENT HAVING FLUIDIC ACTUATING STRUCTURES WITH DIFFERENT FLUIDIC ARCHITECTURES
    39.
    发明申请
    PRINT COMPONENT HAVING FLUIDIC ACTUATING STRUCTURES WITH DIFFERENT FLUIDIC ARCHITECTURES 有权

    公开(公告)号：US20210162735A1

    公开(公告)日：2021-06-03

    申请号：US16957524

    申请日：2019-02-06

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Scott A. LINN ,  James Michael GARDNER ,  John ROSSI

    IPC: B41J2/045

    Abstract: A print component includes an array of fluidic actuation structures including a first column of fluidic actuating structures addressable by a set of actuation addresses, each fluidic actuating structure having a different one of the actuation addresses and having a fluidic architecture type, and a second column of fluidic actuating structures addressable by the set of actuation addresses. Each fluidic actuating structure of the second column has a different one of the actuation addresses and has a same fluidic architecture type as the fluidic actuating structure of the first column having the same address. An address bus communicates the set of addresses to the array of fluidic actuating structures, and a fire signal line communicates a plurality of fire pulse signal types to the array of fluidic actuating structures, the fire pulse signal type depending on the actuation address on the address bus.

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