Resource processing method, apparatus, and terminal

    公开(公告)号:US10915360B2

    公开(公告)日:2021-02-09

    申请号:US16263789

    申请日:2019-01-31

    Abstract: Embodiments of the present application provide a resource processing method, an apparatus, and a terminal. The method includes: receiving, by a first terminal, a first message simultaneously sent by each of at least one second terminal, where the first message is carried on N resources and used to indicate location information of resources on which to-be-sent data is located, and N is a positive integer greater than or equal to 2; and determining, by the first terminal based on the location information of the resources on which the to-be-sent data is located, resources used by the first terminal to send data. Because the first message is carried on the N resources, a probability of collision of the resources used by the second terminal to send the first message is very low.

    Superposition operation circuit and float-voltage digital-to-analog conversion circuit

    公开(公告)号:US10804923B2

    公开(公告)日:2020-10-13

    申请号:US16677810

    申请日:2019-11-08

    Abstract: A superposition operation circuit and a float-voltage digital-to-analog conversion circuit to superpose analog elements according to an indirect current superposition principle, where a voltage follower is implemented using a first operational amplifier such that an output end of the voltage follower is clamped to a voltage that is input to a positive-phase input end, namely, a to-be-superposed analog element. Then a current generation circuit converts a voltage signal to a current signal, a voltage drop for the current signal is generated on a first resistor coupled to an output end of the first operational amplifier, and the voltage drop is superposed on a voltage signal output by the first operational amplifier.

    Output Voltage Regulation Apparatus and Method

    公开(公告)号:US20190294191A1

    公开(公告)日:2019-09-26

    申请号:US16439934

    申请日:2019-06-13

    Abstract: An output voltage regulation apparatus includes a voltage regulation circuit, a control circuit, a power stage circuit, a filtering network, and a feedback network. The feedback network is configured to output a feedback voltage to a feedback voltage node of the control circuit. The voltage regulation circuit is configured to regulate the feedback voltage. The control circuit is configured to switch on or off power transistors in the power stage circuit. The filtering network is configured to perform filtering on an output voltage of the power stage circuit to obtain the regulated output voltage.

    Power Transistor Bias Circuit
    34.
    发明申请

    公开(公告)号:US20190288593A1

    公开(公告)日:2019-09-19

    申请号:US16434603

    申请日:2019-06-07

    Abstract: A direct current-direct current (DC-DC) converter includes an upper transistor, a lower transistor, a first bias circuit and a second bias circuit. A first input end of the first bias circuit is coupled to a first voltage reference, a second input end of the first bias circuit is coupled to a power source (PVDD), and an output end of the first bias circuit is coupled to a gate of the upper transistor to provide a first bias voltage for the gate of the upper transistor. A first input end of the second bias circuit is coupled to a second voltage reference, a second input end of the second bias circuit is coupled to a power ground (PGND), and an output end of the second bias circuit is coupled to a gate of the lower transistor to provide a second bias voltage for the gate of the lower transistor.

    Packet diversion method and deep packet inspection device
    35.
    发明授权
    Packet diversion method and deep packet inspection device 有权
    分组分流方法和深度包检测装置

    公开(公告)号:US08594086B2

    公开(公告)日:2013-11-26

    申请号:US13706063

    申请日:2012-12-05

    CPC classification number: H04L45/74 H04L12/4645 H04L47/2441

    Abstract: A packet diversion method and a DPI device are disclosed in the present invention. The method includes: receiving a packet, where the packet contains a user identifier; according to the user identifier and preset first correspondence between the user identifier and a service type, searching for the service type corresponding to the user identifier in the packet; adding an inner virtual local area network Vlan header to the packet according to the service type, preset second correspondence between a service type and a slave device identifier, and preset third correspondence between a slave device identifier and each bit in a diversion identifier field; and diverting the packet to a corresponding slave device according to the diversion identifier in the diversion identifier field. The inner Vlan header carrying the diversion identifier field is added to the packet, to indicate diversion of the packet in a same cluster.

    Abstract translation: 在本发明中公开了分组分流方法和DPI设备。 该方法包括:接收分组,其中分组包含用户标识符; 根据用户标识符和用户标识符与服务类型之间预设的第一对应关系,搜索与分组中的用户标识符对应的服务类型; 根据服务类型,服务类型和从属设备标识符之间预设的第二对应关系,以及分配标识符字段中的从设备标识符和每个位之间的预设第三对应关系,向分组添加内部虚拟局域网Vlan报头; 并根据转移标识符字段中的转移标识符将分组转发到对应的从设备。 携带分流标识符字段的内部Vlan报头被添加到分组,以指示分组在同一集群中的转移。

    PACKET DIVERSION METHOD AND DEEP PACKET INSPECTION DEVICE
    36.
    发明申请
    PACKET DIVERSION METHOD AND DEEP PACKET INSPECTION DEVICE 有权
    PACKET DIVERSION方法和DEEP PACKET检查装置

    公开(公告)号:US20130094511A1

    公开(公告)日:2013-04-18

    申请号:US13706063

    申请日:2012-12-05

    CPC classification number: H04L45/74 H04L12/4645 H04L47/2441

    Abstract: A packet diversion method and a DPI device are disclosed in the present invention. The method includes: receiving a packet, where the packet contains a user identifier; according to the user identifier and preset first correspondence between the user identifier and a service type, searching for the service type corresponding to the user identifier in the packet; adding an inner virtual local area network Vlan header to the packet according to the service type, preset second correspondence between a service type and a slave device identifier, and preset third correspondence between a slave device identifier and each bit in a diversion identifier field; and diverting the packet to a corresponding slave device according to the diversion identifier in the diversion identifier field. The inner Vlan header carrying the diversion identifier field is added to the packet, to indicate diversion of the packet in a same cluster.

    Abstract translation: 在本发明中公开了分组分流方法和DPI设备。 该方法包括:接收分组,其中分组包含用户标识符; 根据用户标识符和用户标识符与服务类型之间预设的第一对应关系,搜索与分组中的用户标识符对应的服务类型; 根据服务类型,服务类型和从属设备标识符之间预设的第二对应关系,以及分配标识符字段中的从设备标识符和每个位之间的预设第三对应关系,向分组添加内部虚拟局域网Vlan报头; 并根据转移标识符字段中的转移标识符将分组转发到对应的从设备。 携带分流标识符字段的内部Vlan报头被添加到分组,以指示分组在同一集群中的转移。

    Congestion control method, base station, and user equipment

    公开(公告)号:US10785678B2

    公开(公告)日:2020-09-22

    申请号:US16251936

    申请日:2019-01-18

    Abstract: Embodiments of the present disclosure provide example congestion control methods, base stations, and user equipment. After determining that congestion control needs to be performed, a base station determines a congestion control policy, and determines, from UE in coverage of the base station, first UE that needs to perform adjustment according to the congestion control policy. The base station can then send the congestion control policy to the first UE, so that the first UE performs adjustment, to alleviate a congestion status of a PC5 interface. In this process, the base station performs centralized control on all UE in the coverage of the base station.

    Superposition Operation Circuit and Float-Voltage Digital-to-Analog Conversion Circuit

    公开(公告)号:US20200076445A1

    公开(公告)日:2020-03-05

    申请号:US16677810

    申请日:2019-11-08

    Abstract: A superposition operation circuit and a float-voltage digital-to-analog conversion circuit to superpose analog elements according to an indirect current superposition principle, where a voltage follower is implemented using a first operational amplifier such that an output end of the voltage follower is clamped to a voltage that is input to a positive-phase input end, namely, a to-be-superposed analog element. Then a current generation circuit converts a voltage signal to a current signal, a voltage drop for the current signal is generated on a first resistor coupled to an output end of the first operational amplifier, and the voltage drop is superposed on a voltage signal output by the first operational amplifier.

    Power transistor bias circuit
    40.
    发明授权

    公开(公告)号:US10523104B2

    公开(公告)日:2019-12-31

    申请号:US16434603

    申请日:2019-06-07

    Abstract: A direct current-direct current (DC-DC) converter includes an upper transistor, a lower transistor, a first bias circuit and a second bias circuit. A first input end of the first bias circuit is coupled to a first voltage reference, a second input end of the first bias circuit is coupled to a power source (PVDD), and an output end of the first bias circuit is coupled to a gate of the upper transistor to provide a first bias voltage for the gate of the upper transistor. A first input end of the second bias circuit is coupled to a second voltage reference, a second input end of the second bias circuit is coupled to a power ground (PGND), and an output end of the second bias circuit is coupled to a gate of the lower transistor to provide a second bias voltage for the gate of the lower transistor.

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