利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

136 条记录 (耗时 0.035 秒)

    Data transfer scheme using caching and differential compression techniques for reducing network load
    35.
    发明授权
    Data transfer scheme using caching and differential compression techniques for reducing network load 失效
    数据传输方案采用缓存和差分压缩技术来减少网络负载

    公开(公告)号：US07359956B2

    公开(公告)日：2008-04-15

    申请号：US10094462

    申请日：2002-03-11

    申请人： Tatsunori Kanai ,  Toshibumi Seki ,  Kenichiro Yoshii ,  Hideaki Sato ,  Takayuki Miyazawa ,  Haruhiko Toyama ,  Yasuhiro Kimura ,  Hideki Yoshida

    发明人： Tatsunori Kanai ,  Toshibumi Seki ,  Kenichiro Yoshii ,  Hideaki Sato ,  Takayuki Miyazawa ,  Haruhiko Toyama ,  Yasuhiro Kimura ,  Hideki Yoshida

    IPC分类号： G06F15/16 ,  H03M7/34

    CPC分类号： H04L29/06 ,  H04L67/2852 ,  H04L67/2876 ,  H04L69/04

    摘要： In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices. Even when the name corresponding to the data is not registered so that it is impossible to transfer the corresponding name instead of transferring the data, it is possible to reduce the amount of transfer data among the data transfer devices by transferring the compressed data in which this data is expressed in a compressed form by utilizing the name corresponding to the registered reference data.

    摘要翻译： 在使用缓存技术和/或压缩技术的数据传输方案中，能够减少在数据传输设备之间连接的网络的网络负载，数据和它们的名称之间的对应关系被登记在数据传输设备上，并且相应的名称是 而是传送数据，而不是传送数据，对于其对应被登记的那些数据，使得可以减少数据传送装置之间的传送数据量。 即使当与数据相对应的名称没有被登记使得不可能传送相应的名称而不是传送数据时，也可以通过传送数据传送装置中的这种数据的压缩数据来减少传送数据的数量 通过利用与注册的参考数据对应的名称，以压缩形式表示数据。

    Memory management unit and memory management method for controlling a nonvolatile memory and a volatile memory
    36.
    发明授权
    Memory management unit and memory management method for controlling a nonvolatile memory and a volatile memory 有权
    用于控制非易失性存储器和易失性存储器的存储器管理单元和存储器管理方法

    公开(公告)号：US08589639B2

    公开(公告)日：2013-11-19

    申请号：US12884601

    申请日：2010-09-17

    申请人： Hiroto Nakai ,  Tatsunori Kanai

    发明人： Hiroto Nakai ,  Tatsunori Kanai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203

    摘要： According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory.

    摘要翻译： 根据一个实施例，一种存储器管理单元，其将第一存储器作为非易失性存储器和第二存储器控制为易失性存储器，所述存储器管理单元包括：判断所述希望访问的所述第一存储器中的数据是否被存储在所述第二存储器中 当数据未被存储在第二存储器中时，设置错误标志来发布错误数据，并将第二存储器中的要访问的数据读入第二存储器的可用空间。

    Semiconductor memory device and error correcting method
    37.
    发明授权
    Semiconductor memory device and error correcting method 有权
    半导体存储器件和纠错方法

    公开(公告)号：US08429496B2

    公开(公告)日：2013-04-23

    申请号：US12360215

    申请日：2009-01-27

    申请人： Yutaka Yamada ,  Tatsunori Kanai

    发明人： Yutaka Yamada ,  Tatsunori Kanai

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1008 ,  G11C2029/0411

    摘要： A decoding unit is arranged between a reading unit that reads data with an error correction code added from memory cells on a specific one of the first data lines and an output unit that selectively outputs certain data of the read out data. The decoding unit corrects any errors in the data read out by the reading unit in accordance with the error correction code. The data in which the errors are corrected by the decoding unit is written back in the memory cells on the specific first data line.

    摘要翻译： 解码单元设置在读取单元，其读取数据与从特定第一数据线上的存储单元相加的纠错码;以及输出单元，其选择性地输出读出数据的某些数据。 解码单元根据纠错码纠正由读取单元读出的数据中的任何错误。 由解码单元校正错误的数据被写回到特定第一数据线上的存储单元中。

    CACHE MEMORY, COMPUTER SYSTEM AND MEMORY ACCESS METHOD
    38.
    发明申请
    CACHE MEMORY, COMPUTER SYSTEM AND MEMORY ACCESS METHOD 有权
    高速缓存存储器，计算机系统和存储器访问方法

    公开(公告)号：US20120311405A1

    公开(公告)日：2012-12-06

    申请号：US13584182

    申请日：2012-08-13

    申请人： Tatsunori Kanai ,  Yutaka Yamada

    发明人： Tatsunori Kanai ,  Yutaka Yamada

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/1064

    摘要： A cache memory has a data holding unit, having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.

    摘要翻译： 高速缓冲存储器具有数据保持单元，具有多个高速缓存行，每条高速缓存行包括地址区，数据区和脏位，以及给予读取数据的控制器和指示是否已经进行错误校正的校正执行信号 对于读取数据执行读取数据，从存储错误校正编码数据的存储器中读取读取数据，该存储器还将与读取数据相对应的地址信息存储到多个高速缓存行中的任一个的地址区域中，存储读取数据 进入数据区域，并且基于校正执行信号将预定值设置为脏位。

    Method, apparatus, and system for protecting memory
    39.
    发明授权
    Method, apparatus, and system for protecting memory 失效
    用于保护存储器的方法，装置和系统

    公开(公告)号：US07761780B2

    公开(公告)日：2010-07-20

    申请号：US11603037

    申请日：2006-11-22

    申请人： Tatsunori Kanai

    发明人： Tatsunori Kanai

    IPC分类号： G06F11/10

    CPC分类号： G06F21/79 ,  G06F11/1044

    摘要： A parity adder obtains a second data by adding a parity for first data to be written to a memory to the first data. An access-key register holds an access key unique to a source of request. A first operating unit obtains a third data by calculating an XOR between the second data and the access key, the access key being set by the source of request for writing data to the memory. A second operating unit obtains a fourth data by calculating an XOR between the access key and the third data. A syndrome calculator calculates a syndrome from the third data, the access key being set by the source of request for reading data from the memory. A determining unit determines whether to output the third data as the first data, based on calculated syndrome.

    摘要翻译： 奇偶校验加法器通过将要写入存储器的第一数据的奇偶校验与第一数据相加来获得第二数据。 访问密钥寄存器保存对请求源唯一的访问密钥。 第一操作单元通过计算第二数据和访问密钥之间的异或来获得第三数据，该访问密钥由存储器写入数据的请求源设置。 第二操作单元通过计算访问密钥和第三数据之间的异或来获得第四数据。 校正子计算器根据第三数据计算出一个校正子，该访问密钥由存储器读取数据的请求源设置。 确定单元基于所计算的综合器确定是否输出第三数据作为第一数据。