公开(公告)号：US09996489B2

公开(公告)日：2018-06-12

申请号：US14974349

申请日：2015-12-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yaron Shachar ,  Yoav Peleg ,  Alex Tal ,  Alex Umansky ,  Rami Zemach ,  Lixia Xiong ,  Yuchun Lu

IPC: G06F13/00 ,  G06F13/37 ,  G06F5/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/37 ,  G06F5/065 ,  G06F13/1673 ,  G06F13/4234

Abstract: The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.

公开(公告)号：US20160103777A1

公开(公告)日：2016-04-14

申请号：US14974349

申请日：2015-12-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yaron Shachar ,  Yoav Peleg ,  Alex Tal ,  Alex Umansky ,  Rami Zemach ,  Lixia Xiong ,  Yuchun Lu

IPC: G06F13/37 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/37 ,  G06F5/065 ,  G06F13/1673 ,  G06F13/4234

Abstract: The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.

Abstract translation: 本发明涉及一种用于存储一组输入数据流并将数据检索到一组输出数据流的存储器聚合设备，该存储器聚合设备包括：一组先进先出（FIFO）存储器，每一个包括一个输入 和输出; 输入互连器，被配置为根据输入互连矩阵将所述一组输入数据流中的每一个互连到所述一组FIFO存储器的每个输入; 输出互连器，被配置为根据输出互连矩阵将所述一组FIFO存储器的每个输出与所述一组输出数据流中的每一个相互连接; 输入选择器 输出选择器 和一个内存控制器。