Packet processing method and apparatus, communications device, and switching circuit

    公开(公告)号:US11799803B2

    公开(公告)日:2023-10-24

    申请号:US17809166

    申请日:2022-06-27

    CPC classification number: H04L49/90 H04L47/32 H04L47/12

    Abstract: A packet processing method includes: a first device receives a packet from a second device; the first device determines a first queue buffer used to store the packet, and determines a first upper limit value of the first queue buffer based on an available value of a first port buffer and an available value of a global buffer, where the global buffer includes at least one port buffer, the first port buffer is one of the at least one port buffer, the first port buffer includes at least one queue buffer, and the first queue buffer is one of the at least one queue buffer. The first device processes the packet based on the first upper limit value of the first queue buffer, an occupation value of the first queue buffer, and a size of the packet.

    Packet Processing Method and Apparatus, Communications Device, and Switching Circuit

    公开(公告)号:US20220329544A1

    公开(公告)日:2022-10-13

    申请号:US17809166

    申请日:2022-06-27

    Abstract: A packet processing method includes: a first device receives a packet from a second device; the first device determines a first queue buffer used to store the packet, and determines a first upper limit value of the first queue buffer based on an available value of a first port buffer and an available value of a global buffer, where the global buffer includes at least one port buffer, the first port buffer is one of the at least one port buffer, the first port buffer includes at least one queue buffer, and the first queue buffer is one of the at least one queue buffer. The first device processes the packet based on the first upper limit value of the first queue buffer, an occupation value of the first queue buffer, and a size of the packet.

    MEMORY AGGREGATION DEVICE
    4.
    发明申请
    MEMORY AGGREGATION DEVICE 有权
    记忆聚集装置

    公开(公告)号:US20160103777A1

    公开(公告)日:2016-04-14

    申请号:US14974349

    申请日:2015-12-18

    CPC classification number: G06F13/37 G06F5/065 G06F13/1673 G06F13/4234

    Abstract: The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.

    Abstract translation: 本发明涉及一种用于存储一组输入数据流并将数据检索到一组输出数据流的存储器聚合设备,该存储器聚合设备包括:一组先进先出(FIFO)存储器,每一个包括一个输入 和输出; 输入互连器,被配置为根据输入互连矩阵将所述一组输入数据流中的每一个互连到所述一组FIFO存储器的每个输入; 输出互连器,被配置为根据输出互连矩阵将所述一组FIFO存储器的每个输出与所述一组输出数据流中的每一个相互连接; 输入选择器 输出选择器 和一个内存控制器。

    Packet processing method and apparatus, communications device, and switching circuit

    公开(公告)号:US11388114B2

    公开(公告)日:2022-07-12

    申请号:US17171661

    申请日:2021-02-09

    Abstract: A packet processing method includes: a first device receives a packet from a second device; the first device determines a first queue buffer used to store the packet, and determines a first upper limit value of the first queue buffer based on an available value of a first port buffer and an available value of a global buffer, where the global buffer includes at least one port buffer, the first port buffer is one of the at least one port buffer, the first port buffer includes at least one queue buffer, and the first queue buffer is one of the at least one queue buffer. The first device processes the packet based on the first upper limit value of the first queue buffer, an occupation value of the first queue buffer, and a size of the packet.

    SCHEDULING DEVICE
    6.
    发明申请
    SCHEDULING DEVICE 审中-公开
    调度装置

    公开(公告)号:US20160103710A1

    公开(公告)日:2016-04-14

    申请号:US14974320

    申请日:2015-12-18

    CPC classification number: G06F9/4887 G06F9/4881 G06F9/546 H04L49/00

    Abstract: The invention relates to a scheduling device for receiving a set of requests and providing a set of grants to the set of requests, the scheduling device comprising: a lookup vector prepare unit configured to provide a lookup vector prepared set of requests depending on the set of requests and a selection mask and to provide a set of acknowledgements to the set of requests; and a prefix forest unit coupled to the lookup vector prepare unit, wherein the prefix forest unit is configured to provide the set of grants as a function of the lookup vector prepared set of requests and to provide the selection mask based on the set of grants.

    Abstract translation: 本发明涉及一种用于接收一组请求并向该组请求提供一组授权的调度装置,所述调度装置包括:查找向量准备单元,被配置为根据所述一组请求提供准备的请求集合的查找向量 请求和选择掩码,并向该组请求提供一组确认; 以及耦合到所述查找向量准备单元的前缀林单元,其中所述前缀林单元被配置为根据所述查找向量准备的请求集合来提供所述一组授权,并且基于所述一组授权来提供所述选择掩码。

    Packet processing method and apparatus, communications device, and switching circuit

    公开(公告)号:US12224952B2

    公开(公告)日:2025-02-11

    申请号:US18476667

    申请日:2023-09-28

    Abstract: A packet processing method includes: a first device receives a packet from a second device; the first device determines a first queue buffer used to store the packet, and determines a first upper limit value of the first queue buffer based on an available value of a first port buffer and an available value of a global buffer, where the global buffer includes at least one port buffer, the first port buffer is one of the at least one port buffer, the first port buffer includes at least one queue buffer, and the first queue buffer is one of the at least one queue buffer. The first device processes the packet based on the first upper limit value of the first queue buffer, an occupation value of the first queue buffer, and a size of the packet.

    PACKET PROCESSING METHOD AND APPARATUS, COMMUNICATIONS DEVICE, AND SWITCHING CIRCUIT

    公开(公告)号:US20240022527A1

    公开(公告)日:2024-01-18

    申请号:US18476667

    申请日:2023-09-28

    CPC classification number: H04L49/90 H04L47/32 H04L47/12

    Abstract: A packet processing method includes: a first device receives a packet from a second device; the first device determines a first queue buffer used to store the packet, and determines a first upper limit value of the first queue buffer based on an available value of a first port buffer and an available value of a global buffer, where the global buffer includes at least one port buffer, the first port buffer is one of the at least one port buffer, the first port buffer includes at least one queue buffer, and the first queue buffer is one of the at least one queue buffer. The first device processes the packet based on the first upper limit value of the first queue buffer, an occupation value of the first queue buffer, and a size of the packet.

    PACKET PROCESSING METHOD AND APPARATUS, COMMUNICATIONS DEVICE, AND SWITCHING CIRCUIT

    公开(公告)号:US20210168095A1

    公开(公告)日:2021-06-03

    申请号:US17171661

    申请日:2021-02-09

    Abstract: A packet processing method includes: a first device receives a packet from a second device; the first device determines a first queue buffer used to store the packet, and determines a first upper limit value of the first queue buffer based on an available value of a first port buffer and an available value of a global buffer, where the global buffer includes at least one port buffer, the first port buffer is one of the at least one port buffer, the first port buffer includes at least one queue buffer, and the first queue buffer is one of the at least one queue buffer. The first device processes the packet based on the first upper limit value of the first queue buffer, an occupation value of the first queue buffer, and a size of the packet.

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