公开(公告)号：US20170255561A1

公开(公告)日：2017-09-07

申请号：US15062824

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Alaa R. Alameldeen ,  Rajat Agarwal

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0868 ,  G06F2212/401

Abstract: Technologies for increasing associativity of a direct mapped cache using compression include an apparatus that includes a memory to store data blocks, a cache to store a subset of the data blocks in various of physical cache blocks, and a memory management unit (MMU). The MMU is to compress data blocks associated with locations of the main memory that are mapped to a physical cache block and write the compressed data blocks to the physical cache block if the combined size of the compressed blocks satisfies a threshold size. Other embodiments are also described and claimed.

公开(公告)号：US09417879B2

公开(公告)日：2016-08-16

申请号：US13924334

申请日：2013-06-21

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Eugene Gorbatov ,  Zeshan A. Chishti

IPC: G06F9/38 ,  G06F9/50

CPC classification number: G06F9/3836 ,  G06F9/5077 ,  G06F2209/507 ,  Y02D10/22 ,  Y02D10/36

Abstract: Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared.

Abstract translation: 管理可重构处理器内核的系统和方法。 一个示例性处理系统包括多个处理器核心; 包括多个状态位的控制寄存器，每个状态位指示对应的处理器核心的状态，所述控制寄存器还包括多个禁止位，每个禁止位指示相应的处理器核心是否被允许与其他处理器核心合并 ; 以及核心管理逻辑，用于响应于确定与所述第一处理器核相对应的第一状态位被设置来合并第一处理器核和第二处理器核，清除与所述第一处理器核相对应的第一禁止位， 对应于第二处理器核的状态位被清除，并且与第二处理器核相对应的第二禁止位被清除。