公开(公告)号：US11886984B2

公开(公告)日：2024-01-30

申请号：US17398302

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Amit Bleiweiss ,  Gal Leibovich ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag

IPC: G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06F9/30

CPC classification number: G06N3/063 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30043 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240028883A1

公开(公告)日：2024-01-25

申请号：US18359270

申请日：2023-07-26

Applicant: Intel Corporation

Inventor： Tomer Schwartz ,  Ehud Cohen ,  Uzi Sarel ,  Amitai Armon ,  Yaniv Fais ,  Lev Faivishevsky ,  Amit Bleiweiss ,  Yahav Shadmiy ,  Jacob Subag

IPC: G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.

公开(公告)号：US20230394305A1

公开(公告)日：2023-12-07

申请号：US18325744

申请日：2023-05-30

Applicant: Intel Corporation

Inventor： Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Jeremie Dreyfuss ,  Amit Bleiweiss ,  Tomer Schwartz ,  Raanan Yonatan Yehezkel Rohekar ,  Michael Behar ,  Amitai Armon ,  Uzi Sarel

IPC: G06N3/08 ,  G06N20/00 ,  G06N20/10

CPC classification number: G06N3/08 ,  G06N20/10 ,  G06N20/00

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220012163A1

公开(公告)日：2022-01-13

申请号：US17483431

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Niranjan Hasabnis ,  Justin Gottschlich ,  Jeremie Dreyfuss ,  Amitai Armon ,  Itamar Ben-Ari ,  Oren David Kimhi

IPC: G06F11/36 ,  G06F8/73 ,  G06F8/40

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to detect code defects. An example apparatus includes repository interface circuitry to retrieve code repositories corresponding to a programming language of interest, tree generating circuitry to generate parse trees corresponding to code blocks contained in the code repositories, directed acyclic graph (DAG) circuitry to generate DAGs corresponding to respective ones of the parse trees, the DAGs including control flow information and data flow information, abstraction generating circuitry to abstract the DAGs, invariant identification circuitry to extract invariants from the abstracted DAGs, and DAG comparison circuitry to cluster respective ones of the extracted invariants to identify respective ones of the abstracted DAGs with common invariants.

公开(公告)号：US20210350585A1

公开(公告)日：2021-11-11

申请号：US17344639

申请日：2021-06-10

Applicant: INTEL CORPORATION

Inventor： Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Jeremie Dreyfuss ,  Gal Novik ,  Gal Leibovich ,  Tomer Schwartz ,  Ehud Cohen ,  Lev Faivishevsky ,  Uzi Sarel ,  Amitai Armon ,  Yahav Shadmiy

IPC: G06T9/00 ,  H04N19/42 ,  G06N3/04 ,  H04N19/436 ,  G06N3/08

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US11037330B2

公开(公告)日：2021-06-15

申请号：US15482725

申请日：2017-04-08

Applicant: Intel Corporation

Inventor： Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Jeremie Dreyfuss ,  Gal Novik ,  Gal Leibovich ,  Tomer Schwartz ,  Ehud Cohen ,  Lev Faivishevsky ,  Uzi Sarel ,  Amitai Armon ,  Yahav Shadmiy

IPC: G06T9/00 ,  H04N19/42 ,  G06N3/04 ,  H04N19/436 ,  G06N3/08

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210049804A1

公开(公告)日：2021-02-18

申请号：US17006253

申请日：2020-08-28

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06T15/00 ,  G06N3/02 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180314932A1

公开(公告)日：2018-11-01

申请号：US15499898

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Tomer Schwartz ,  Ehud Cohen ,  Uzi Sarel ,  Amitai Armon ,  Yaniv Fais ,  Lev Faivishevsky ,  Amit Bleiweiss ,  Yahav Shadmiy ,  Jacob Subag

IPC: G06N3/08 ,  G06T1/20 ,  G06F7/60

CPC classification number: G06N3/06 ,  G06N3/0454

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to generate synthetic data for a generative adversarial network (GAN) using the plurality of execution units. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180082212A1

公开(公告)日：2018-03-22

申请号：US15270057

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Lev Faivishevsky ,  Amitai Armon

IPC: G06N99/00 ,  G06F15/82

CPC classification number: G06N20/00 ,  G06F15/82

Abstract: An optimization of running time for performing a machine learning algorithm on a processor architecture may be performed and include determining a plurality of parameters to be configured in the machine learning algorithm, and initiating, in the optimization, a plurality of iterations of performance of the machine learning algorithm by the processor architecture. Each of the iterations may include detecting a running time of an immediately preceding one of the iterations, changing a value of one of the parameters used in the immediately preceding iteration to form a new set of values, where the value is changed based on the detected running time of the immediately preceding iteration and according to a downhill simplex algorithm. An optimal set of values for the parameters may be determined based on the plurality of iterations to realize a minimum running time to complete performance of the machine learning algorithm by the processor architecture.