公开(公告)号：US20210073138A1

公开(公告)日：2021-03-11

申请号：US16950233

申请日：2020-11-17

Applicant: Intel Corporation

Inventor： Karthik KUMAR ,  Thomas WILLHALM ,  Francesc GUIM BERNAT ,  Brian J. SLECHTA

IPC: G06F12/0891 ,  G06F9/30

Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.

公开(公告)号：US20200379922A1

公开(公告)日：2020-12-03

申请号：US16995481

申请日：2020-08-17

Applicant: Intel Corporation

Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT

IPC: G06F12/14 ,  G06F12/0813 ,  G06F12/0891 ,  G06F12/06

Abstract: Examples described herein relate to a network device apparatus that includes a packet processing circuitry configured to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, cause transmission of the memory access request to the different device. In some examples, the memory access request comprises an identifier of a requester of the memory access request and the identifier comprises a Process Address Space identifier (PASID) and wherein the configuration that a redirection operation is permitted to be performed for a memory access request is based at least on the identifier. In some examples, the packet processing circuitry is to: based on configuration of a redirection operation not to be performed for the memory access request, cause transmission of the memory access request to a device identified in the memory access request.

公开(公告)号：US20200259763A1

公开(公告)日：2020-08-13

申请号：US16859792

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Patrick CONNOR ,  Patrick G. KUTCH ,  John J. BROWNE ,  Alexander BACHMUTSKY

IPC: H04L12/911 ,  H04L12/26 ,  H04L12/24

Abstract: Examples described herein relate to a device configured to allocate memory resources for packets received by the network interface based on received configuration settings. In some examples, the device is a network interface. Received configuration settings can include one or more of: latency, memory bandwidth, timing of when the content is expected to be accessed, or encryption parameters. In some examples, memory resources include one or more of: a cache, a volatile memory device, a storage device, or persistent memory. In some examples, based on a configuration settings not being available, the network interface is to perform one or more of: dropping a received packet, store the received packet in a buffer that does not meet the configuration settings, or indicate an error. In some examples, configuration settings are conditional where the settings are applied if one or more conditions is met.

公开(公告)号：US20200242258A1

公开(公告)日：2020-07-30

申请号：US16845885

申请日：2020-04-10

Applicant: Intel Corporation

Inventor： Ned SMITH ,  Kshitij A. DOSHI ,  Francesc GUIM BERNAT ,  Kapil SOOD ,  Tarun VISWANATHAN

IPC: G06F21/60 ,  G06F15/173 ,  H04L9/32

Abstract: Examples herein relate to an interface selectively providing access to a memory region for a work request from an entity by providing selective access to a physical address of the memory region and selective access to a cryptographic key for use by a memory controller to access the memory region. In some examples, providing selective access to a physical address conversion is based on one or more of: validation of a certificate received with the work request and an identifier of the entity being associated with a process with access to the memory region. Access to the memory region can be specified to be one or more of: create, read, update, delete, write, or notify. A memory region can be a page or sub-page sized region. Different access rights can be associated with different sub-portions of the memory region, wherein the access rights comprise one or more of: create, read, update, delete, write, or notify.

公开(公告)号：US20200226009A1

公开(公告)日：2020-07-16

申请号：US16836650

申请日：2020-03-31

Applicant: Intel Corporation

Inventor： Alexander BACHMUTSKY ,  Raghu KONDAPALLI ,  Francesc GUIM BERNAT ,  Vadim SUKHOMLINOV

IPC: G06F9/54 ,  G06F8/41 ,  G06F21/52 ,  G06F12/10

Abstract: Examples described herein relate to requesting execution of a workload by a next function with data transport overhead tailored based on memory sharing capability with the next function. In some examples, data transport overhead is one or more of: sending a memory address pointer, virtual memory address pointer or sending data to the next function. In some examples, the memory sharing capability with the next function is based on one or more of: whether the next function shares an enclave with a sender function, the next function shares physical memory domain with a sender function, or the next function shares virtual memory domain with a sender function. In some examples, selection of the next function from among multiple instances of the next function based on one or more of: sharing of memory domain, throughput performance, latency, cost, load balancing, or service legal agreement (SLA) requirements.

公开(公告)号：US20190102090A1

公开(公告)日：2019-04-04

申请号：US15719729

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Thomas WILLHALM ,  Mark SCHMISSEUR

IPC: G06F3/06 ,  G06F9/48

Abstract: A memory controller method and apparatus, which includes a modification of at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via a first memory set interface and over a channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via a second memory set interface and over the channel. Furthermore, an issuance of a request to at least one of the first memory set in accordance with the modified first timing scheme or the second memory set in accordance with the modified second timing scheme may be included.

公开(公告)号：US20190042372A1

公开(公告)日：2019-02-07

申请号：US16012525

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT ,  Mark A. SCHMISSEUR ,  Mustafa HAJEER ,  Thomas WILLHALM

IPC: G06F11/14 ,  G06F11/20 ,  H04L29/06 ,  H04L29/08

Abstract: An in-memory database is mirrored in persistent memory in nodes in a computer cluster for redundancy. Data can be recovered from persistent memory in a node that is powered down through the use of out-of-band techniques.

公开(公告)号：US20180089248A1

公开(公告)日：2018-03-29

申请号：US15280939

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Daniel A. RIVAS BARRAGAN ,  Kshitij A. DOSHI ,  Mark A. SCHMISSEUR ,  Steen LARSEN

IPC: G06F17/30

CPC classification number: G06F16/23 ,  G06F16/275

Abstract: Fabric supported replication enables hardware replication and hardware-assisted software replication of objects on behalf of replication software. Software specifies to a communication fabric of a storage system which objects to replicate and where and how to replicate them. A storage protocol defines which storage operations modify replicated objects. Alternatively, nodes in the communication fabric infer whether storage operations modify replicated objects. Either way, the fabric logic automatically propagates replicated objects and updates to replicated objects to replica nodes based on the software specification. The fabric logic initiates message flows between the replica nodes in order to perform the hardware replication and hardware-assisted software replication.

公开(公告)号：US20180007134A1

公开(公告)日：2018-01-04

申请号：US15199572

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Daniel RIVAS BARRAGAN ,  Kshitij A. DOSHI ,  Mark A. SCHMISSEUR ,  Steen LARSEN

IPC: H04L29/08 ,  G06F3/06 ,  H04L12/931

Abstract: Fabric encapsulated resilient storage is hardware-assisted resilient storage in which the reliability capabilities of a storage server are abstracted and managed transparently by a host fabric interface (HFI) to a switch. The switch abstracts the reliability capabilities of a storage server into a level of resilience in a hierarchy of levels of resilience. The resilience levels are accessible by clients as a quantifiable characteristic of the storage server. The resilience levels are used by the switch fabric to filter which storage servers store objects responsive to client requests to store objects at a specified level of resilience.

公开(公告)号：US20240185714A1

公开(公告)日：2024-06-06

申请号：US18556367

申请日：2021-09-24

Applicant: INTEL CORPORATION

Inventor： Satish JHA ,  Kathiravetpillai SIVANESAN ,  S M Iftekharul ALAM ,  Kuilin Clark CHEN ,  Kshitij DOSHI ,  Leonardo GOMES BALTAR ,  Francesc GUIM BERNAT ,  Arvind MERWADAY ,  Markus Dominik MUECK ,  Suman A. SEHRA ,  Vesh Raj SHARMA BANJADE ,  Soo Jin TAN

IPC: G08G1/087 ,  G01C21/34 ,  G08G1/00 ,  G08G1/09

CPC classification number: G08G1/087 ,  G01C21/34 ,  G08G1/09 ,  G08G1/20

Abstract: The disclosure relates to systems, methods, and devices for managing traffic through a road segment and/or intersection. The traffic management system may place traffic objects in a collaboration group for coordinating movements in the road segment and/or intersection in response to a received indication that an emergency vehicle has a planned route that includes the road segment and/or intersection. The traffic management system may determine a movement plan for each traffic object in the collaboration group based on received measurements about the road segment and the planned route of the emergency vehicle. The traffic management system may control a transmitter to send the movement plan to each traffic object in the collaboration group.