公开(公告)号：US20250097120A1

公开(公告)日：2025-03-20

申请号：US18966019

申请日：2024-12-02

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Kshitij A. DOSHI ,  Brinda GANESH ,  Timothy VERRALL

IPC: H04L41/16 ,  G06N3/04 ,  G06N5/04 ,  H04L41/0816 ,  H04L41/5009 ,  H04L41/5019 ,  H04L41/5051

Abstract: Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.

公开(公告)号：US20240143505A1

公开(公告)日：2024-05-02

申请号：US18393793

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Amruta MISRA ,  Ajay RAMJI ,  Rajendrakumar CHINNAIYAN ,  Chris MACNAMARA ,  Karan PUTTANNAIAH ,  Pushpendra KUMAR ,  Vrinda KHIRWADKAR ,  Sanjeevkumar Shankrappa ROKHADE ,  John J. BROWNE ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Farheena Tazeen SYEDA

IPC: G06F12/0811

CPC classification number: G06F12/0811

Abstract: Methods and apparatus for dynamic selection of super queue size for CPUs with higher number of cores. An apparatus includes a plurality of compute modules, each module including a plurality of processor cores with integrated first level (L1) caches and a shared second level (L2) cache, a plurality of Last Level Caches (LLCs) or LLC blocks and a plurality of memory interface blocks interconnect via a mesh interconnect. A compute module is configured to arbitrate access to the shared L2 cache and enqueue L2 cache misses in a super queue (XQ). The compute module further is configured to dynamically adjust the size of the XQ during runtime operations. The compute module tracks parameters comprising an L2 miss rate or count and LLC hit latency and adjusts the XQ size as a function of these parameters. A lookup table using the L2 miss rate/count and LLC hit latency may be implemented to dynamically select the XQ size.

公开(公告)号：US20240134726A1

公开(公告)日：2024-04-25

申请号：US18537703

申请日：2023-12-12

Applicant: Intel Corporation

Inventor： Akhilesh S. THYAGATURU ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Adrian HOBAN ,  Marek PIOTROWSKI

IPC: G06F9/54 ,  G06F1/20

CPC classification number: G06F9/548 ,  G06F1/206

Abstract: A method is described. The method includes invoking one of more functions from a set of API functions that expose the current respective cooling states of different, respective cooling devices for different components of a hardware platform. The method includes orchestrating concurrent execution of multiple applications on the hardware platform in view of the current respective cooling states. The method includes, in order to prepare the hardware platform for the concurrent execution of the multiple applications, prior to the concurrent execution of the multiple applications, sending one or more commands to the hardware platform to change a cooling state of at least one of the cooling devices.

公开(公告)号：US20240134432A1

公开(公告)日：2024-04-25

申请号：US18537697

申请日：2023-12-12

Applicant: Intel Corporation

Inventor： Akhilesh S. THYAGATURU ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Jonathan KYLE ,  Marek PIOTROWSKI

IPC: G06F1/20 ,  G06F9/455

CPC classification number: G06F1/206 ,  G06F9/45558 ,  G06F2009/45591

Abstract: A method is claimed. The method includes receiving information associated with a software application's workflow. The method includes receiving information that describes a platform's current power consumption state and current thermal state. The method includes selecting platform components to support execution of the workflow. The method includes prior to execution of the workflow upon the selected platform components, estimating a thermal impact to the platform's current thermal state as a consequence of the workflow's execution upon the selected platform components. The method includes determining a change to be made to a thermal cooling system of the platform in response to the estimating and causing the change to be made to the thermal cooling system prior to execution of at least a portion of the workflow on the platform.

公开(公告)号：US20240022111A1

公开(公告)日：2024-01-18

申请号：US18375034

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Akhilesh S. THYAGATURU ,  Francesc GUIM BERNAT ,  Patrick CONNOR ,  Vinodh GOPAL ,  Mohit Kumar GARG

IPC: H02J13/00

CPC classification number: H02J13/00028

Abstract: A method is described. The method includes receiving a request. The method includes allocating and/or configuring hardware to execute the request in accordance with an energy related input specified by a sender of the request. The method includes causing execution of the request in accordance with the energy related input.

公开(公告)号：US20240004709A1

公开(公告)日：2024-01-04

申请号：US17809968

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN ,  Kshitij A. DOSHI ,  Rita H. WOUHAYBI ,  Francesc GUIM BERNAT ,  Marcos CARRANZA

IPC: G06F9/50

CPC classification number: G06F9/5005

Abstract: Examples relate to a concept for software application container hardware resource allocation, and in particular to sidecar apparatuses, sidecar devices, methods for a software application container sidecars, a resource management controller apparatus, a resource management controller device, and corresponding computer programs and computer systems. A sidecar apparatus comprises interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions to obtain information on hardware resources desired by a software application container from the software application container, and to provide a request for changing the hardware resources allocated to the software application container to another entity capable of influencing an allocation of hardware resources to the software application container.

公开(公告)号：US20230185760A1

公开(公告)日：2023-06-15

申请号：US17549727

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Susanne M. BALLE ,  Duane E. GALBI ,  Andrzej KURIATA ,  Sundar NADATHUR ,  Nagabhushan CHITLUR ,  Francesc GUIM BERNAT ,  Alexander BACHMUTSKY

IPC: G06F15/78

CPC classification number: G06F15/7889 ,  G06F15/7821 ,  G06F15/7871 ,  G06F2015/768

Abstract: Methods, apparatus, and software and for hardware microservices accelerated in other processing units (XPUs). The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). The FPGA is configured to implement one or more Hardware (HW) accelerator functions associated with HW microservices. Execution of microservices is split between a software front-end that executes on the SOC and a hardware backend comprising the HW accelerator functions. The software front-end offloads a portion of a microservice and/or associated workload to the HW microservice backend implemented by the accelerator functions. An XPU or FPGA proxy is used to provide the microservice front-ends with shared access to HW accelerator functions, and schedules/multiplexes access to the HW accelerator functions using, e.g., telemetry data generated by the microservice front-ends and/or the HW accelerator functions. The platform may be an infrastructure processing unit (IPU) configured to accelerate infrastructure operations.

公开(公告)号：US20230023229A1

公开(公告)日：2023-01-26

申请号：US17952835

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT ,  Alexander BACHMUTSKY ,  Susanne M. BALLE ,  Andrzej KURIATA ,  Nagabhushan CHITLUR

IPC: G06F3/06

Abstract: In a server system, a host computing platform can have a processing unit separate from the host processor to detect and respond to failure of the host processor. The host computing platform includes a memory to store data for the host processor. The processing unit has an interface to the host processor and the memory and an interface to a network external to the host processor and has access to the memory. In response to detection of failure of the host processor, the processing unit migrates data from the memory to another memory or storage.

公开(公告)号：US20220272012A1

公开(公告)日：2022-08-25

申请号：US17744034

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： S M Iftekharul ALAM ,  Ned SMITH ,  Vesh Raj SHARMA BANJADE ,  Satish C. JHA ,  Christian MACIOCCO ,  Mona VIJ ,  Kshitij A. DOSHI ,  Srikathyayani SRIKANTESWARA ,  Francesc GUIM BERNAT ,  Maruti GUPTA HYDE ,  Alexander BACHMUTSKY

IPC: H04L43/0811 ,  H04L43/0882 ,  H04L43/091 ,  H04L43/062

Abstract: Examples described herein relate to dynamically composing an application as a monolithic implementation or two or more microservices based on telemetry data. In some examples, based on composition of an application as two or more microservices, at least one connection between microservices based on telemetry data is adjusted. In some examples, a switch can be configured to perform forwarding of communications between microservices based on the adjusted at least one connection between microservices.

公开(公告)号：US20220222117A1

公开(公告)日：2022-07-14

申请号：US17709289

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Patrick G. KUTCH ,  Francesc GUIM BERNAT ,  Andrey CHILIKIN ,  Brian P. JOHNSON

IPC: G06F9/50

Abstract: Examples describe techniques to expose application telemetry in a virtualized execution environment. Examples include a plurality of application executing within the virtualized execution environment writing telemetry data to a memory associated with virtual devices of a hardware device. Examples also include an orchestrator to read the telemetry data from the memory and use the telemetry data to make resource allocation decisions.