公开(公告)号：US20190042909A1

公开(公告)日：2019-02-07

申请号：US15821123

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Huseyin E. Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Raghavan Kumar ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/063

Abstract: In one embodiment, a processor comprises a first neuro-synaptic core comprising first circuitry to configure the first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter.

公开(公告)号：US09961019B2

公开(公告)日：2018-05-01

申请号：US14579729

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Ram K. Krishnamurthy ,  Yejoong Kim

IPC: H04L12/933

CPC classification number: H04L49/109 ,  H04L45/60 ,  H04L49/60

Abstract: A packet-switched reservation request to be associated with a first data stream is received. A communication mode is selected. The communication mode is to be either a circuit-switched mode or a packet-switched mode. At least a portion of the first data stream is communicated in accordance with the communication mode.

公开(公告)号：US09787571B2

公开(公告)日：2017-10-10

申请号：US14579845

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Vivek K. De ,  Ram K. Krishnamurthy ,  Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H04L12/26 ,  H04L12/727 ,  H04L12/933 ,  H04L12/773 ,  G06F15/78

CPC classification number: H04L45/121 ,  G06F15/7825 ,  H04L43/0852 ,  H04L45/125 ,  H04L45/24 ,  H04L45/60 ,  H04L49/109

Abstract: A router of a network-on-chip receives delay information associated with a plurality of links of the network-on-chip. The router determines at least one link of a data path based on the delay information.

公开(公告)号：US20160182393A1

公开(公告)日：2016-06-23

申请号：US14579303

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Ram K. Krishnamurthy ,  Aaron T. Stillmaker

IPC: H04L12/863 ,  H04L12/935 ,  H04L12/26 ,  H04L12/911

CPC classification number: H04L47/625 ,  G06F15/7825 ,  H04L12/6402 ,  H04L47/72 ,  H04L49/30

Abstract: A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.

Abstract translation: 接收到第一分组交换预约请求。 根据尽力而为的通信方案，通过第一电路交换信道来传送与第一分组交换预约请求相关联的数据。 接收第二分组交换预约请求。 根据保证的吞吐量通信方案，通过第二电路交换信道来传送与第二分组交换预约请求相关联的数据。

公开(公告)号：US20160179728A1

公开(公告)日：2016-06-23

申请号：US14574352

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Gregory K. Chen

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  H04L12/54 ,  H04L49/10

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

Abstract translation: 一种装置包括包括输入端口和输出端口的第一端口组。 该装置还包括多个第二端口组。 每个第二端口组包括耦合到第一端口组的输出端口的输入端口和耦合到第一端口组的输入端口的输出端口。 多个第二端口组将以第一最大带宽进行通信，并且第一端口组将以高于第一最大带宽的第二最大带宽进行通信。

公开(公告)号：US11868296B2

公开(公告)日：2024-01-09

申请号：US17701593

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Gregory K. Chen

IPC: H05K7/10 ,  G06F13/40 ,  H04L49/10 ,  H04L12/54

CPC classification number: G06F13/4022 ,  H04L12/54 ,  H04L49/10

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

公开(公告)号：US11699681B2

公开(公告)日：2023-07-11

申请号：US16727779

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Hui Jae Yoo ,  Van H. Le ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Gregory K. Chen ,  Ram Krishnamurthy

IPC: H01L25/065 ,  G11C11/407

CPC classification number: H01L25/0657 ,  G11C11/407 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

公开(公告)号：US11625584B2

公开(公告)日：2023-04-11

申请号：US16443548

申请日：2019-06-17

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Gregory K. Chen ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Ram Krishnamurthy

IPC: G06N3/063 ,  G06N3/084 ,  G06F7/544

Abstract: Examples described herein relate to a neural network whose weights from a matrix are selected from a set of weights stored in a memory on-chip with a processing engine for generating multiply and carry operations. The number of weights in the set of weights stored in the memory can be less than a number of weights in the matrix thereby reducing an amount of memory used to store weights in a matrix. The weights in the memory can be generated in training using gradients from back propagation. Weights in the memory can be selected using a tabulation hash calculation on entries in a table.

公开(公告)号：US20220214988A1

公开(公告)日：2022-07-07

申请号：US17701593

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Gregory K. Chen

IPC: G06F13/40 ,  H04L49/10 ,  H04L12/54

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

公开(公告)号：US11347477B2

公开(公告)日：2022-05-31

申请号：US16586648

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Raghavan Kumar ,  Ram Krishnamurthy

IPC: G06F7/544 ,  G06F17/16 ,  G06F7/498 ,  G06F12/02 ,  G06F9/30

Abstract: A memory circuit includes a number (X) of multiply-accumulate (MAC) circuits that are dynamically configurable. The MAC circuits can either compute an output based on computations of X elements of the input vector with the weight vector, or to compute the output based on computations of a single element of the input vector with the weight vector, with each element having a one bit or multibit length. A first memory can hold the input vector having a width of X elements and a second memory can store the weight vector. The MAC circuits include a MAC array on chip with the first memory.