公开(公告)号：US10897364B2

公开(公告)日：2021-01-19

申请号：US15846045

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Vivek De ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Khondker Ahmed ,  Sriram Vangal ,  Vaibhav Vaidya ,  Turbo Majumder ,  Christopher Schaef ,  Suhwan Kim ,  Xiaosen Liu ,  Nachiket Desai

IPC: H04L9/32

Abstract: Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

公开(公告)号：US20190317536A1

公开(公告)日：2019-10-17

申请号：US16450873

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Harish Krishnamurthy ,  Krishnan Ravichandran ,  Vivek De ,  Scott Chiu ,  Claudia Patricia Barrera Gonzalez ,  Jing Han ,  Rajasekhara Madhusudan Narayana Bhatla

IPC: G05F1/56 ,  G05F1/67 ,  G05F1/46

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

公开(公告)号：US20170187187A1

公开(公告)日：2017-06-29

申请号：US14998328

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Sally Amin ,  Sergio Carlo ,  Harish Krishnamurthy ,  Christopher Schaef ,  Vaibhav Vaidya

IPC: H02J3/38 ,  H02J7/00

Abstract: A power regulator includes a plurality of harvester switches, each coupled to receive a separate energy source, a plurality of load switches, each coupled to supply power to a separate load, an inductor to store energy received from one or more energy sources and release the energy to supply the power to one or more loads and a controller to control charging of the inductor via activation of one or more of the harvester switches and discharging of the inductor via activation of one or more of the load switches.