公开(公告)号：US11080202B2

公开(公告)日：2021-08-03

申请号：US15721800

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Niall D. McDonnell ,  Christopher MacNamara ,  John J. Browne ,  Andrew Cunningham ,  Brendan Ryan ,  Patrick Fleming ,  Namakkal N. Venkatesan ,  Bruce Richardson ,  Tomasz Kantecki ,  Sean Harte ,  Pierre Laurent

IPC: G06F12/08 ,  G06F12/0888 ,  G06F12/0806 ,  G06F12/0817 ,  G06F12/0837 ,  G06F9/00

Abstract: A computing apparatus, including: a processor; a pointer to a counter memory location; and a lazy increment counter engine to: receive a stimulus to update the counter; and lazy increment the counter including issuing a weakly-ordered increment directive to the pointer.

公开(公告)号：US20210034546A1

公开(公告)日：2021-02-04

申请号：US17041768

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Weigang Li ,  Changzheng Wei ,  John Barry ,  Maryam Tahhan ,  Jonas Alexander Svennebring ,  Niall D. McDonnell ,  Alexander Leckey ,  Patrick Fleming ,  Christopher MacNamara ,  John Joseph Browne

IPC: G06F12/14 ,  G06F13/28 ,  G06F13/16 ,  G06F21/53 ,  G06F21/60 ,  G06F21/79

Abstract: There is disclosed a computing apparatus, including: a memory; a memory encryption controller to encrypt at least a region of the memory; and a network interface to communicatively couple the computing apparatus to a remote host; wherein the memory encryption controller is configured to send an encrypted packet decryptable via an encryption key directly from the memory to the remote host via the network interface, bypassing a network protocol stack.

公开(公告)号：US10606751B2

公开(公告)日：2020-03-31

申请号：US15201348

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： Andrew Cunningham ,  Mark D. Gray ,  Alexander Leckey ,  Chris MacNamara ,  Stephen T. Palermo ,  Pierre Laurent ,  Niall D. McDonnell ,  Tomasz Kantecki ,  Patrick Fleming

IPC: G06F12/0811 ,  G06F12/0831

Abstract: An input/output (I/O) device arranged to receive an information element including a payload, determine control information from the information element, classify the information element based on the control information, and issue a write to one of a plurality of computer-readable media based on the classification of the information element, the write to cause the payload to be written to the one of the plurality of computer-readable media.

公开(公告)号：US20190044893A1

公开(公告)日：2019-02-07

申请号：US16024774

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Bruce Richardson ,  Chris MacNamara ,  Patrick Fleming ,  Tomasz Kantecki ,  Ciara Loftus ,  John J. Browne ,  Patrick Connor

IPC: H04L12/861 ,  H04L12/879

Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.