中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.017 seconds)

    Traffic management
    1.
    发明授权
    Traffic management 有权

    公开(公告)号：US10091122B2

    公开(公告)日：2018-10-02

    申请号：US15396488

    申请日：2016-12-31

    Applicant: INTEL CORPORATION

    Inventor： Cristian Florin Dumitrescu ,  Andrey Chilikin ,  Pierre Laurent ,  Kannan Babu Ramia ,  Sravanthi Tangeda

    IPC: H04L12/869 ,  H04L12/815 ,  H04L12/851 ,  H04L12/819 ,  H04L12/813 ,  H04L12/803

    Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.

    TRAFFIC MANAGEMENT
    2.
    发明申请
    TRAFFIC MANAGEMENT 审中-公开
    交通管理

    公开(公告)号：US20170070356A1

    公开(公告)日：2017-03-09

    申请号：US15269295

    申请日：2016-09-19

    Applicant: INTEL CORPORATION

    Inventor： Cristian Florin Dumitrescu ,  Andrey Chilikin ,  Pierre Laurent ,  Kannan Babu Ramia ,  Sravanthi Tangeda

    IPC: H04L12/14 ,  H04L12/801 ,  H04L12/863 ,  H04L12/865 ,  H04L12/819 ,  H04L12/815

    CPC classification number: H04L47/60 ,  H04L12/1439 ,  H04L47/10 ,  H04L47/125 ,  H04L47/20 ,  H04L47/21 ,  H04L47/215 ,  H04L47/22 ,  H04L47/2408 ,  H04L47/2433 ,  H04L47/2441 ,  H04L47/39 ,  H04L47/50 ,  H04L47/527 ,  H04L47/623 ,  H04L47/6255 ,  H04L47/627 ,  H04L47/6275

    Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.

    Abstract translation: 一个实施例提供一种网络设备。 网络设备包括：处理器，包括至少一个处理器核心; 网络接口，被配置为以线路速率发送和接收分组; 存储器，被配置为存储调度器分层数据结构; 和调度器模块。 调度器模块被配置为预取下一个活动管道结构，包括在分级数据结构中的下一个主动管道结构，更新当前管道和相关联的子端口的信用，至少基于当前管道识别下一个活动业务类别 部分地，在当前的管道数据结构上，选择与所识别的下一个活动业务类别相关联的下一个队列，并且如果可用的流量整形令牌桶信用和可用业务类别，则可以从所选择的下一个队列调度下一个分组以供网络接口传输 信用额度大于或等于下一个信用额度。

    TECHNOLOGIES FOR SCALABLE PACKET RECEPTION AND TRANSMISSION
    3.
    发明申请
    TECHNOLOGIES FOR SCALABLE PACKET RECEPTION AND TRANSMISSION 审中-公开

    公开(公告)号：US20190327190A1

    公开(公告)日：2019-10-24

    申请号：US16460424

    申请日：2019-07-02

    Applicant: Intel Corporation

    Inventor： John J. Browne ,  Tomasz Kantecki ,  Chris MacNamara ,  Pierre Laurent ,  Sean Harte

    IPC: H04L12/879 ,  H04L12/46 ,  H04L12/861 ,  H04L12/43 ,  H04L12/927 ,  H04L12/935

    Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.

    PACKET FLOW CLASSIFICATION
    5.
    发明申请
    PACKET FLOW CLASSIFICATION 审中-公开

    公开(公告)号：US20180103129A1

    公开(公告)日：2018-04-12

    申请号：US15677564

    申请日：2017-08-15

    Applicant: Intel Corporation

    Inventor： Cristian Florin F. Dumitrescu ,  Namakkal N. Venkatesan ,  Pierre Laurent ,  Bruce Richardson

    IPC: H04L29/06 ,  H04L12/743 ,  H04L12/64

    CPC classification number: H04L69/22 ,  H04L12/6418 ,  H04L45/7453

    Abstract: Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key. The computing device handles processing of received data packets such that a fetch classification operation is performed by the flow classification module on the first received data packet while a non-fetch classification operation is performed by the flow classification module on a second received data packet.

    HARDWARE PROCESSORS AND METHODS FOR TIGHTLY-COUPLED HETEROGENEOUS COMPUTING
    6.
    发明申请
    HARDWARE PROCESSORS AND METHODS FOR TIGHTLY-COUPLED HETEROGENEOUS COMPUTING 有权
    硬件处理器和轻巧耦合异构计算的方法

    公开(公告)号：US20160378715A1

    公开(公告)日：2016-12-29

    申请号：US14752047

    申请日：2015-06-26

    Applicant: Intel Corporation

    Inventor： Chang Yong Kang ,  Pierre Laurent ,  Hari K. Tadepalli ,  Prasad M. Ghatigar ,  T.J. O'Dwyer ,  Serge Zhilyaev

    IPC: G06F15/80

    CPC classification number: G06F15/8061 ,  G06F9/30036 ,  G06F9/3814 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3877 ,  G06F13/16 ,  G06F13/4059

    Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.

    Abstract translation: 描述了与紧耦合异构计算有关的方法和设备。 在一个实施例中，硬件处理器并行地包括多个执行单元，用于将多个执行单元的输入连接到第一缓冲器和多个存储器组的输出并连接多个存储体的输入的开关和 与第一缓冲器，多个存储体和多个执行单元的输出并联的多个第二缓冲器，以及具有连接到多个第二缓冲器的输出的输入的卸载引擎。

    Parallelized authentication encoding
    8.
    发明授权
    Parallelized authentication encoding 有权

    公开(公告)号：US10140458B2

    公开(公告)日：2018-11-27

    申请号：US15093200

    申请日：2016-04-07

    Applicant: Intel Corporation

    Inventor： Chang Yong Kang ,  Pierre Laurent

    IPC: G06F12/14 ,  G06F21/60 ,  G06F9/30 ,  G06F9/38 ,  G06F21/64

    Abstract: A processing system implementing techniques for parallelized authentication encoding is provided. In one embodiment, the processing system includes an accumulator, a register representing a pipeline stage and a processing core coupled to the accumulator and to the register. The processing core is to split an input message into a first input stream and a second input stream. For each input stream, the processing core is further to add, to the accumulator, a data block from the input stream. Contents of the accumulator multiplied by a squared nonce value are stored in the register and a result of applying a modulo reduction operation to the contents of the register is stored in the accumulator. Thereupon, an authentication tag for the input message is generated based on the result stored in the accumulator and the contents of the register.

    TECHNOLOGIES FOR COORDINATING ACCESS TO DATA PACKETS IN A MEMORY
    10.
    发明申请
    TECHNOLOGIES FOR COORDINATING ACCESS TO DATA PACKETS IN A MEMORY 审中-公开

    公开(公告)号：US20170366477A1

    公开(公告)日：2017-12-21

    申请号：US15185864

    申请日：2016-06-17

    Applicant: Intel Corporation

    Inventor： John J. Browne ,  Seán Harte ,  Tomasz Kantecki ,  Pierre Laurent ,  Chris MacNamara

    IPC: H04L12/861 ,  H04L12/935 ,  H04L12/933

    CPC classification number: H04L49/9057 ,  H04L49/102 ,  H04L49/3063

    Abstract: Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.

Patent Agency Ranking