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    SYSTEMS AND METHODS FOR PERFORMING 16-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS
    32.
    发明申请
    SYSTEMS AND METHODS FOR PERFORMING 16-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS 有权

    公开(公告)号：US20210286620A1

    公开(公告)日：2021-09-16

    申请号：US17216566

    申请日：2021-03-29

    Applicant: Intel Corporation

    Inventor： Alexander F. HEINECKE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Raanan SADE ,  Menachem ADELMAN ,  Zeev SPERBER ,  Amit GRADSTEIN ,  Simon RUBANOVICH

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.

    EFFICIENT IMPLEMENTATION OF COMPLEX VECTOR FUSED MULTIPLY ADD AND COMPLEX VECTOR MULTIPLY
    37.
    发明申请
    EFFICIENT IMPLEMENTATION OF COMPLEX VECTOR FUSED MULTIPLY ADD AND COMPLEX VECTOR MULTIPLY 审中-公开

    公开(公告)号：US20190303142A1

    公开(公告)日：2019-10-03

    申请号：US15941531

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Raanan SADE ,  Thierry PONS ,  Amit GRADSTEIN ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Robert VALENTINE ,  Eyal Oz-Sinay

    IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38

    Abstract: Disclosed embodiments relate to efficient complex vector multiplication. In one example, an apparatus includes execution circuitry, responsive to an instruction having fields to specify multiplier, multiplicand, and summand complex vectors, to perform two operations: first, to generate a double-even multiplicand by duplicating even elements of the specified multiplicand, and to generate a temporary vector using a fused multiply-add (FMA) circuit having A, B, and C inputs set to the specified multiplier, the double-even multiplicand, and the specified summand, respectively, and second, to generate a double-odd multiplicand by duplicating odd elements of the specified multiplicand, to generate a swapped multiplier by swapping even and odd elements of the specified multiplier, and to generate a result using a second FMA circuit having its even product negated, and having A, B, and C inputs set to the swapped multiplier, the double-odd multiplicand, and the temporary vector, respectively.

    SYSTEMS, APPARATUSES, AND METHODS FOR DATA SPECULATION EXECUTION
    39.
    发明申请
    SYSTEMS, APPARATUSES, AND METHODS FOR DATA SPECULATION EXECUTION 审中-公开

    公开(公告)号：US20190121644A1

    公开(公告)日：2019-04-25

    申请号：US14582859

    申请日：2014-12-24

    Applicant: Intel Corporation

    Inventor： Elmoustapha OULD-AHMED-VALL ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Milind B. GIRKAR

    IPC: G06F9/38 ,  G06F9/35

    Abstract: Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for DSX comprises execution hardware to execute instructions to begin and end a data speculative execution (DSX) and speculative instructions during the DSX, and DSX tracking hardware to track speculative memory accesses and detect ordering violations in a DSX of speculative instructions using a sequence number, addresses of instruction accesses, and whether an instruction being tracked is a write, and to trigger a mis-speculation upon an ordering violation.

    SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS SPECIFYING TERNARY TILE LOGIC OPERATIONS
    40.
    发明申请
    SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS SPECIFYING TERNARY TILE LOGIC OPERATIONS 审中-公开

    公开(公告)号：US20190042260A1

    公开(公告)日：2019-02-07

    申请号：US16131376

    申请日：2018-09-14

    Applicant: Intel Corporation

    Inventor： Elmoustapha OULD-AHMED-VALL ,  Christopher J. HUGHES ,  Bret TOLL ,  Dan BAUM ,  Raanan SADE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Alexander F. HEINECKE

    IPC: G06F9/38 ,  G06F17/16 ,  G06F9/30

    Abstract: Disclosed embodiments relate to systems and methods for performing instructions specifying ternary tile operations. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction specifying a ternary tile operation, and locations of destination and first, second, and third source matrices, each of the matrices having M rows by N columns; and execution circuitry to respond to the decoded instruction by, for each equal-sized group of K elements of the specified first, second, and third source matrices, generate K results by performing the ternary tile operation in parallel on K corresponding elements of the specified first, second, and third source matrices, and store each of the K results to a corresponding element of the specified destination matrix, wherein corresponding elements of the specified source and destination matrices occupy a same relative position within their associated matrix.

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