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公开(公告)号：US20210165942A1
公开(公告)日：2021-06-03
申请号：US17168945
申请日：2021-02-05
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
IPC: G06F30/3323 , G06F11/07 , G06F11/34 , G06F30/39
Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.
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公开(公告)号：US11010477B2
公开(公告)日：2021-05-18
申请号：US15784615
申请日：2017-10-16
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari
Abstract: Described herein are hardware monitors arranged to detect illegal firmware instructions in a firmware binary image using a hardware design and one or more formal assertions. The hardware monitors include monitor and detection logic configured to detect when an instantiation of the hardware design has started and/or stopped execution of the firmware and to detect when the instantiation of the hardware design has decoded an illegal firmware instruction. The hardware monitors also include assertion evaluation logic configured to determine whether the firmware binary image comprises an illegal firmware instruction by evaluating one or more assertions that assert that if a stop of firmware execution has been detected, that a decode of an illegal firmware instruction has (or has not) been detected. The hardware monitor may be used by a formal verification tool to exhaustively verify that the firmware boot image does not comprise an illegal firmware instruction, or during simulation to detect illegal firmware instructions in a firmware boot image.
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公开(公告)号：US20200349313A1
公开(公告)日：2020-11-05
申请号：US16930424
申请日：2020-07-16
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
IPC: G06F30/3323 , G06F11/07 , G06F11/34 , G06F30/39
Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.
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34.发明申请公开(公告)号：US20200150964A1
公开(公告)日：2020-05-14
申请号：US16743586
申请日：2020-01-15
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
Abstract: Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.
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公开(公告)号：US10580511B2
公开(公告)日：2020-03-03
申请号：US15340726
申请日：2016-11-01
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.
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Patent Agency Ranking
公开(公告)号：US20190272350A1
公开(公告)日：2019-09-05
申请号：US16419734
申请日：2019-05-22
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.
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公开(公告)号：US20190272349A1
公开(公告)日：2019-09-05
申请号：US16414594
申请日：2019-05-16
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.
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公开(公告)号：US20190258765A1
公开(公告)日：2019-08-22
申请号：US16399218
申请日：2019-04-30
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Sam Elliott
IPC: G06F17/50
Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.
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公开(公告)号：US10331831B2
公开(公告)日：2019-06-25
申请号：US15340450
申请日：2016-11-01
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in an instantiation of the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the instantiation of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.
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公开(公告)号：US10089138B2
公开(公告)日：2018-10-02
申请号：US15297331
申请日：2016-10-19
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari
Abstract: Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design using a counter and an indexed table. The data structure includes a counter that keeps track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions using the counter; and control logic that verifies a transaction response has been received in the correct order (e.g. corresponds to the oldest in-flight transaction) based on the age information in the table.
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