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公开(公告)号：US10817301B2
公开(公告)日：2020-10-27
申请号：US16009358
申请日：2018-06-15
发明人： Luca Iuliano , Simon Nield , Yoong-Chert Foo , Ollie Mower
摘要： Methods and parallel processing units for avoiding inter-pipeline data hazards wherein inter-pipeline data hazards are identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. Then when a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted (e.g. incremented) to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted (e.g. decremented) to indicate that the hazard related to the primary instruction has been resolved. When a secondary instruction is output by the decoder for execution, the secondary instruction is stalled in a queue associated with the appropriate instruction pipeline if at least one counter associated with the primary instructions from which it depends indicates that there is a hazard related to the primary instruction.
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公开(公告)号：US20180365058A1
公开(公告)日：2018-12-20
申请号：US16011241
申请日：2018-06-18
发明人： Simon Nield , Yoong-Chert Foo , Adam de Grasse , Luca Iuliano
CPC分类号： G06F9/4881 , G06F7/575 , G06F9/3001 , G06F9/3016 , G06F9/3836 , G06F9/3851
摘要： A method of activating scheduling instructions within a parallel processing unit is described. The method includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.
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公开(公告)号：US20180365057A1
公开(公告)日：2018-12-20
申请号：US16011093
申请日：2018-06-18
发明人： Simon Nield , Yoong-Chert Foo , Adam de Grasse , Luca Iuliano
摘要： A method of scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state, and checking, by an instruction controller, if an ALU targeted by the decoded instruction is a primary instruction pipeline. If the targeted ALU is a primary instruction pipeline, a list associated with the primary instruction pipeline is checked to determine whether the scheduled task is already included in the list. If the scheduled task is already included in the list, the decoded instruction is sent to the primary instruction pipeline.
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公开(公告)号：US20180365009A1
公开(公告)日：2018-12-20
申请号：US16010935
申请日：2018-06-18
发明人： Simon Nield , Yoong-Chert Foo , Adam de Grasse , Luca Iuliano
摘要： A method of activating scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state and checking, by an instruction controller, if a swap flag is set in the decoded instruction. If the swap flag in the decoded instruction is set, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.
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公开(公告)号：US20180088989A1
公开(公告)日：2018-03-29
申请号：US15713803
申请日：2017-09-25
发明人： Simon Nield , Adam de Grasse , Luca Iuliano , Ollie Mower , Yoong-Chert Foo
CPC分类号： G06F9/4881 , G06F1/329 , G06F9/5027 , G06F2209/483 , G06F2209/486 , G06T1/20 , Y02D10/24
摘要： A method of scheduling tasks within a GPU or other highly parallel processing unit is described which is both age-aware and wakeup event driven. Tasks which are received are added to an age-based task queue. Wakeup event bits for task types, or combinations of task types and data groups, are set in response to completion of a task dependency and these wakeup event bits are used to select an oldest task from the queue that satisfies predefined criteria.
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公开(公告)号：US11698790B2
公开(公告)日：2023-07-11
申请号：US17523633
申请日：2021-11-10
发明人： Luca Iuliano , Simon Nield , Yoong-Chert Foo , Ollie Mower
CPC分类号： G06F9/3861 , G06F9/3016 , G06F9/3834 , G06F9/3838 , G06F9/3867 , G06F9/3889
摘要： Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved. When a secondary instruction is output by the decoder for execution, the secondary instruction is stalled in a queue associated with the appropriate instruction pipeline if at least one counter associated with the primary instructions from which it depends indicates that there is a hazard related to the primary instruction.
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公开(公告)号：US11656908B2
公开(公告)日：2023-05-23
申请号：US17220849
申请日：2021-04-01
发明人： Luca Iuliano , Simon Nield , Yoong-Chert Foo , Ollie Mower , Jonathan Redshaw
IPC分类号： G06F9/50 , G06F12/084 , G06F12/02 , G06F12/0842 , G06F9/48 , G06F9/54 , G06F12/00
CPC分类号： G06F9/5016 , G06F9/4881 , G06F9/505 , G06F9/5022 , G06F9/544 , G06F12/0223 , G06F12/084 , G06F12/0842 , G06F12/00 , G06F12/02
摘要： A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.
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公开(公告)号：US11531545B2
公开(公告)日：2022-12-20
申请号：US17108389
申请日：2020-12-01
发明人： Simon Nield , Yoong-Chert Foo , Adam de Grasse , Luca Iuliano
摘要： A method of activating scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state and checking, by an instruction controller, if a swap flag is set in the decoded instruction. If the swap flag in the decoded instruction is set, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.
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公开(公告)号：US11500677B2
公开(公告)日：2022-11-15
申请号：US17087837
申请日：2020-11-03
发明人： Ollie Mower , Yoong-Chert Foo
摘要： A method of synchronizing a group of scheduled tasks within a parallel processing unit into a known state is described. The method uses a synchronization instruction in a scheduled task which triggers, in response to decoding of the instruction, an instruction decoder to place the scheduled task into a non-active state and forward the decoded synchronization instruction to an atomic ALU for execution. When the atomic ALU executes the decoded synchronization instruction, the atomic ALU performs an operation and check on data assigned to the group ID of the scheduled task and if the check is passed, all scheduled tasks having the particular group ID are removed from the non-active state.
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公开(公告)号：US20220075652A1
公开(公告)日：2022-03-10
申请号：US17529004
申请日：2021-11-17
发明人： Simon Nield , Yoong-Chert Foo , Adam de Grasse , Luca Iuliano
摘要： A method of activating scheduling instructions within a parallel processing unit includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.
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