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公开(公告)号:US20220366204A1
公开(公告)日:2022-11-17
申请号:US17742873
申请日:2022-05-12
Applicant: Infineon Technologies AG
Inventor: Frank Pueschner , Jens Pohl , Peter Stampka
IPC: G06K19/07
Abstract: A chip card biometric sensor component having a carrier, a biometric sensor arranged on or in the carrier, a control logic, which is arranged on or in the carrier and is coupled to the biometric sensor, and at least one light-emitter, which is arranged on or in the carrier or in an opening of the carrier and is connected to the control logic and is controllable by the latter.
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公开(公告)号:US10395157B2
公开(公告)日:2019-08-27
申请号:US14483174
申请日:2014-09-11
Applicant: Infineon Technologies AG
Inventor: Frank Pueschner , Thomas Spoettl , Jens Pohl , Peter Stampka
IPC: H01L21/56 , G06K19/077 , H01L23/00 , H01L23/31
Abstract: A method for producing a smart card module arrangement includes: arranging a smart card module on a first carrier layer, wherein the first carrier layer is free of a prefabricated smart card module receptacle cutout for receiving the smart card module. The smart card module includes: a substrate; a chip on the substrate; a first mechanical reinforcement structure between the chip and the substrate. The first mechanical reinforcement structure covers at least one part of a surface of the chip. The method further includes applying a second carrier layer to the smart card module, wherein the second carrier layer is free of a prefabricated smart card module receptacle cutout for receiving the smart card module; and at least one of laminating or pressing the first carrier layer with the second carrier layer, such that the smart card module is enclosed by the first carrier layer and the second carrier layer.
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公开(公告)号:US20170206448A1
公开(公告)日:2017-07-20
申请号:US15406832
申请日:2017-01-16
Applicant: Infineon Technologies AG
Inventor: Frank Pueschner , Peter Stampka , Siegfried Hoffner , Jens Pohl
IPC: G06K19/077
CPC classification number: G06K19/07775 , G06K19/0776 , G06K19/07779 , G06K19/07794
Abstract: A chip card is provided. The chip card may include a chip card substrate and an antenna structure disposed in or over the chip card substrate, the antenna structure including a wire arranged to form a first antenna portion configured to contactlessly couple to a chip card external device and a second antenna portion configured to couple to a chip antenna, wherein the wire may include an electrically conductive material coated with an electrically insulating material, wherein the wire of the first antenna portion may be arranged such that a direction of laying progress of the wire of at least some adjacent wire portions are opposite to each other, such that the at least some adjacent wire portions may form a capacitor, wherein the isolation material of the at least some adjacent wire portions may be physically contacting each other.
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公开(公告)号:US20170154853A1
公开(公告)日:2017-06-01
申请号:US15364306
申请日:2016-11-30
Applicant: Infineon Technologies AG
Inventor: Frank Pueschner , Peter Stampka
IPC: H01L23/544 , H01L21/304 , H01L21/3065 , H01L21/78
CPC classification number: H01L23/544 , H01L21/304 , H01L21/3065 , H01L21/78 , H01L22/30 , H01L22/34 , H01L2223/54426 , H01L2223/5446 , Y02P80/30
Abstract: A method for singulating a multiplicity of chips is provided. Each chip includes a substrate, an active region arranged at least one of in or on the substrate, at least one electronic component being formed in said active region, and a dielectric above the active region. The method includes forming at least one first trench between the chips. The at least one first trench is formed through the dielectric and the active regions and extends into the substrate. The method further includes sawing the substrate material from the opposite side of the substrate relative to the first trench along a sawing path corresponding to the course of at least one first trench, such that at least one second trench is formed. The width of the at least one first trench is less than or equal to the width of the at least one second trench.
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