公开(公告)号：US20160131743A1

公开(公告)日：2016-05-12

申请号：US14931183

申请日：2015-11-03

Applicant: Infineon Technologies AG

Inventor： David Addison ,  Dian Tresna Nugraha ,  Andre Roger ,  Romain Ygnace

IPC: G01S7/35

CPC classification number: G01S7/354 ,  G01S7/414 ,  G01S7/415 ,  G01S13/34 ,  G01S13/931 ,  G01S2007/356

Abstract: An example relates to a method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results without a second group of the FFT results.

Abstract translation: 一个例子涉及一种用于处理雷达信号的方法，其中所述雷达信号包括由至少一个雷达天线接收的数字化数据，所述方法包括：（i）基于所接收的数字化数据确定FFT结果; 和（ii）存储第一组FFT结果，而没有第二组FFT结果。

公开(公告)号：US11802938B2

公开(公告)日：2023-10-31

申请号：US17072365

申请日：2020-10-16

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Markus Bichl ,  Farhan Bin Khalid ,  Romain Ygnace

IPC: G01S7/02 ,  G01S7/35

CPC classification number: G01S7/023 ,  G01S7/354 ,  G01S7/356

Abstract: A radar device is provided that is arranged for conducting an interference detection and mitigation based on received and sampled radar signals and storing interference-mitigated data; conducting an FFT on the interference-mitigated data and storing FF-transformed data; conducting a compression on the FF-transformed data into compressed data; and storing the compressed data in a memory. Also, a method for operating such radar device is suggested.

公开(公告)号：US20220410912A1

公开(公告)日：2022-12-29

申请号：US17822957

申请日：2022-08-29

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Farhan Bin Khalid ,  Romain Ygnace

IPC: B60W50/00

Abstract: An electronic control unit includes a signal input circuit configured to receive a sensor signal from a radar sensor or from a lidar sensor and a processing circuit configured to determine a first condition based on a first representation of the sensor signal, and to generate an activation signal in response to the first condition.

公开(公告)号：US20210258021A1

公开(公告)日：2021-08-19

申请号：US16793149

申请日：2020-02-18

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Markus Bichl ,  Romain Ygnace

IPC: H03M7/30 ,  G01S7/295 ,  G01S7/35

Abstract: A processor having a hardware decompressor configured to pad a non-equidistant data set, which is data received at irregular time intervals, with one or more of a predefined value, wherein the data is radar or optical sensor data; and a Fourier transform engine configured to receive the padded non-equidistant data set directly and continuously per data set from the hardware decompressor, and to FFT process the received padded non-equidistant data set.

公开(公告)号：US20210116533A1

公开(公告)日：2021-04-22

申请号：US17072365

申请日：2020-10-16

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Markus Bichl ,  Farhan Bin Khalid ,  Romain Ygnace

IPC: G01S7/02 ,  G01S7/35

Abstract: A radar device is provided that is arranged for conducting an interference detection and mitigation based on received and sampled radar signals and storing interference-mitigated data; conducting an FFT on the interference-mitigated data and storing FF-transformed data; conducting a compression on the FF-transformed data into compressed data; and storing the compressed data in a memory. Also, a method for operating such radar device is suggested.

公开(公告)号：US10929949B2

公开(公告)日：2021-02-23

申请号：US16367635

申请日：2019-03-28

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Pedro Costa ,  Andre Roger ,  Romain Ygnace

IPC: G06T1/60 ,  G06F12/02 ,  G06T3/40

Abstract: A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.

公开(公告)号：US10852409B2

公开(公告)日：2020-12-01

申请号：US15081404

申请日：2016-03-25

Applicant: Infineon Technologies AG

Inventor： Dian Tresna Nugraha ,  Andre Roger ,  Romain Ygnace

IPC: G01S13/34 ,  G06F13/28 ,  G01S13/931 ,  G01S7/35

Abstract: A device for processing radar signals is suggested, said device comprising a DMA engine, a buffer and a processing stage, wherein the DMA engine is arranged for conducting a read access to a memory, wherein such read access comprises at least two data entries, and for filling the buffer by resorting the at least two data entries, wherein the processing stage is arranged for processing the data stored in the buffer.

公开(公告)号：US10796617B2

公开(公告)日：2020-10-06

申请号：US13916446

申请日：2013-06-12

Applicant: Infineon Technologies AG

Inventor： Andre' Roger ,  Romain Ygnace

IPC: G06F15/80 ,  G09G5/00 ,  G09G3/20 ,  G06T1/60

Abstract: An implementation relates to a device for processing an image data stream. The device may include a first processing unit and a second processing unit for receiving the image data stream. The first processing unit may be arranged for providing a first data stream, the first data stream has a reduced bandwidth compared to the image data stream. The second processing unit may arranged for providing a second data stream, the second data stream has a reduced bandwidth compared to the image data stream.

公开(公告)号：US20190339360A1

公开(公告)日：2019-11-07

申请号：US16402268

申请日：2019-05-03

Applicant: Infineon Technologies AG

Inventor： Romain Ygnace ,  David Addison ,  Markus Bichl ,  Dian Tresna Nugraha ,  Andre Roger

IPC: G01S7/35

Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.

公开(公告)号：US20190129002A1

公开(公告)日：2019-05-02

申请号：US16159957

申请日：2018-10-15

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Romain Ygnace

IPC: G01S7/292 ,  G01S13/93 ,  G01S7/288

Abstract: A radar device including at least three subcircuits, wherein each subcircuit has a cascade input port and a cascade output port and is chained such that the cascade output port of a first subcircuit is connected to the cascade input port of a subsequent subcircuit, the cascade input port of the last subcircuit of the chain is connected to the cascade output port of its preceding subcircuit, and the cascade output port of the last subcircuit of the chain is connectable to an external device, and wherein the at least three subcircuits are configured to conduct a radar computation in a distributed manner such that intermediate results are conveyed towards the last subcircuit of the chain which is configured to combine these results and supply them towards its cascade output port.