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公开(公告)号：US20190339360A1
公开(公告)日：2019-11-07
申请号：US16402268
申请日：2019-05-03
Applicant: Infineon Technologies AG
Inventor： Romain Ygnace , David Addison , Markus Bichl , Dian Tresna Nugraha , Andre Roger
IPC: G01S7/35
Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.
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公开(公告)号：US09841497B2
公开(公告)日：2017-12-12
申请号：US14296886
申请日：2014-06-05
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Romain Ygnace , David Addison
CPC classification number: G01S13/02 , G01S7/352 , G01S13/343 , G01S13/42 , G01S13/931 , G01S2007/356
Abstract: A device is suggested for processing input data received by several antennas, the device including a processing unit including a buffer and at least one multiplier, wherein the processing unit is configured to calculate a second stage FFT result based on input data received by a first antenna, multiply the second stage FFT result for the first antenna with a first compensation value, and store the result in the buffer. The processing unit is further configured to calculate a second stage FFT result based on input data received by a second antenna, multiply the second stage FFT for the second antenna with a second compensation value, and add the result to the value stored in the buffer.
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公开(公告)号：US20240311320A1
公开(公告)日：2024-09-19
申请号：US18183317
申请日：2023-03-14
Applicant: Infineon Technologies AG
Inventor： David Addison , Dyson Wilkes , Markus Bichl
CPC classification number: G06F13/28 , G01S13/58 , G01S7/285 , G01S7/356 , G06F2213/28
Abstract: A radar system includes a radio frequency (RF) receiver configured to receive radar data at a plurality of receive antennae. A fast Fourier transform (FFT) circuit is coupled to the RF receiver. The FFT circuit is configured to perform a FFT on the radar data to provide a stream of complex values. The stream of complex values includes a plurality of Range-Doppler coordinate pairs that pertain to the plurality of receive antennae. A memory is coupled to the FFT circuit. The memory is configured to store three-dimensional (3D) radar data. A Direct Memory Access circuit (DMA) is coupled to the memory.
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公开(公告)号：US20240310480A1
公开(公告)日：2024-09-19
申请号：US18183292
申请日：2023-03-14
Applicant: Infineon Technologies AG
Inventor： David Addison , Dyson Wilkes , Markus Bichl , Sandeep Vangipuram
CPC classification number: G01S7/354 , G01S7/356 , G01S13/584
Abstract: A radar system including a direct memory access (DMA). The DMA includes a bus interface including control/status registers and data-in/data-out registers. The DMA also includes potential object queue memory coupled to the bus interface, and a potential object queue logic coupled to the potential object queue memory. The DMA also includes boundary checking circuitry configured to detect whether any portion of a DMA read configuration is greater than a maximum range bin or less than a minimum range bin. The boundary checking circuitry detects whether any portion of the DMA read configuration is greater than a maximum Doppler bin or less than a minimum Doppler bin.
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公开(公告)号：US10222470B2
公开(公告)日：2019-03-05
申请号：US14931361
申请日：2015-11-03
Applicant: Infineon Technologies AG
Inventor： David Addison , Dian Tresna Nugraha , Andre Roger , Romain Ygnace
Abstract: A method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results, wherein the first group of FFT results comprises at least two portions, wherein a first portion of FFT results is stored with a first accuracy and a second portion of FFT results is stored with a second accuracy.
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Patent Agency Ranking
公开(公告)号：US20150355319A1
公开(公告)日：2015-12-10
申请号：US14296886
申请日：2014-06-05
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Romain Ygnace , David Addison
CPC classification number: G01S13/02 , G01S7/352 , G01S13/343 , G01S13/42 , G01S13/931 , G01S2007/356
Abstract: A device is suggested for processing input data received by several antennas, the device including a processing unit including a buffer and at least one multiplier, wherein the processing unit is configured to calculate a second stage FFT result based on input data received by a first antenna, multiply the second stage FFT result for the first antenna with a first compensation value, and store the result in the buffer. The processing unit is further configured to calculate a second stage FFT result based on input data received by a second antenna, multiply the second stage FFT for the second antenna with a second compensation value, and add the result to the value stored in the buffer.
Abstract translation: 提出了一种用于处理由几个天线接收的输入数据的装置，该装置包括包括缓冲器和至少一个乘法器的处理单元，其中处理单元被配置为基于由第一天线接收的输入数据来计算第二级FFT结果 ，将第一天线的第二级FFT结果乘以第一补偿值，并将结果存储在缓冲器中。 处理单元还被配置为基于由第二天线接收的输入数据来计算第二级FFT结果，将第二天线的第二级FFT乘以第二补偿值，并将结果添加到存储在缓冲器中的值。
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7.发明公开公开(公告)号：US20240353529A1
公开(公告)日：2024-10-24
申请号：US18404133
申请日：2024-01-04
Applicant: Infineon Technologies AG
Inventor： Dyson Wilkes , Moustafa Samy Abdelkhalek Ahmed Emara , David Addison
CPC classification number: G01S7/356 , G01S7/2883 , G01S13/584
Abstract: Some aspects of the present disclosure relate a radar system including a radio frequency (RF) receiver that receives radar data on a plurality of receive antennas. A fast Fourier transform (FFT) circuit is coupled to the RF receiver. The FFT circuit performs a FFT on the radar data to provide a plurality of Range-Doppler coordinate pairs that pertain to the plurality of receive antennas. An integration block is coupled to the FFT circuit, and sums multiple Range-Doppler coordinate pairs for respective Doppler bins to provide a plurality of Range-Doppler sums. The integration block also sums multiple Range-Doppler sums within the plurality of Range-Doppler sums to provide an integration result. The multiple Range-Doppler coordinate pairs that are summed are spaced apart from one another by a Doppler offset.
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公开(公告)号：US20240310481A1
公开(公告)日：2024-09-19
申请号：US18183263
申请日：2023-03-14
Applicant: Infineon Technologies AG
Inventor： David Addison , Dyson Wilkes , Markus Bichl , Sandeep Vangipuram
CPC classification number: G01S7/356 , G01S13/584
Abstract: A baseband processor including a fast Fourier transform (FFT) circuit having an FFT input and an FFT output. A first processing path having a first processing path input and a first processing path output. The first processing path including a memory coupled to the FFT output and the first processing path input via a first bus. A Direct Memory Access (DMA) coupled between the memory and the first processing path output. The DMA coupled to the memory via a second bus. A second processing path arranged in parallel with the first processing path. The second processing path including a detection circuit having a detection circuit input coupled to the FFT output and having a detection circuit output coupled to the DMA.
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公开(公告)号：US20240302431A1
公开(公告)日：2024-09-12
申请号：US18179593
申请日：2023-03-07
Applicant: Infineon Technologies AG
Inventor： David Addison , Dyson Wilkes
IPC: G01R31/317 , G01R31/3185 , G01R31/319
CPC classification number: G01R31/31718 , G01R31/31703 , G01R31/31853 , G01R31/31926
Abstract: Systems, methods, and circuitry are provided for a sorting array. In one example, a sorting array element includes an output register and control circuitry. The output register is configured to store an output value. In response to a cell under test (CUT) load signal the output register stores a CUT value and in response to a first register shift signal from a previous sorting array element the output register stores contents of an output register of the previous sorting array element. The control circuitry is configured to generate the CUT load signal and a second register shift signal for a subsequent sorting array element based on relative magnitudes of the CUT value, the output value, and an output value stored in the output register of the previous sorting array element.
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公开(公告)号：US11525885B2
公开(公告)日：2022-12-13
申请号：US16402268
申请日：2019-05-03
Applicant: Infineon Technologies AG
Inventor： Romain Ygnace , David Addison , Markus Bichl , Dian Tresna Nugraha , Andre Roger
IPC: G01S7/35
Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.
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