公开(公告)号：US20220270974A1

公开(公告)日：2022-08-25

申请号：US17684163

申请日：2022-03-01

Applicant: INTEL CORPORATION

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/762 ,  H01L21/765 ,  H01L25/065 ,  H01L29/06

Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

公开(公告)号：US11222837B2

公开(公告)日：2022-01-11

申请号：US16838556

申请日：2020-04-02

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L23/498 ,  H01L25/16 ,  H01L23/42 ,  H01L49/02 ,  H01L21/48

Abstract: A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.

公开(公告)号：US11114394B2

公开(公告)日：2021-09-07

申请号：US16536997

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Jianyong Xie ,  Sujit Sharan ,  Robert L. Sankman

IPC: H01L23/66 ,  H01L23/15 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01P3/08 ,  H01P11/00 ,  H01L23/14

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an article having a substrate, a semiconductor die thereon, a routing carrier attached to the substrate, and a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier. In selected examples, the article is made by manufacturing a substrate, attaching a semiconductor die to the substrate, fabricating a routing carrier comprising a transmission pathway, and integrating the routing carrier into the substrate.

公开(公告)号：US20210043588A1

公开(公告)日：2021-02-11

申请号：US16536997

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Jianyong Xie ,  Sujit Sharan ,  Robert L. Sankman

IPC: H01L23/66 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01P3/08 ,  H01P11/00

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an article having a substrate, a semiconductor die thereon, a routing carrier attached to the substrate, and a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier. In selected examples, the article is made by manufacturing a substrate, attaching a semiconductor die to the substrate, fabricating a routing carrier comprising a transmission pathway, and integrating the routing carrier into the substrate.

公开(公告)号：US20200243448A1

公开(公告)日：2020-07-30

申请号：US15774306

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Zhiguo Qian ,  Jianyong Xie ,  Kemal Aygun

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.