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    Dielectric-filled trench isolation of vias
    5.
    发明授权
    Dielectric-filled trench isolation of vias 有权

    公开(公告)号：US11296031B2

    公开(公告)日：2022-04-05

    申请号：US16769548

    申请日：2018-03-30

    Applicant: INTEL CORPORATION

    Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

    IPC: H01L23/538 ,  H01L21/762 ,  H01L29/06 ,  H01L21/765 ,  H01L25/065

    Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

    Dielectric-filled trench isolation of vias
    7.
    发明授权
    Dielectric-filled trench isolation of vias 有权

    公开(公告)号：US11887932B2

    公开(公告)日：2024-01-30

    申请号：US17684163

    申请日：2022-03-01

    Applicant: INTEL CORPORATION

    Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

    IPC: H01L23/538 ,  H01L21/762 ,  H01L25/065 ,  H01L29/06 ,  H01L21/765

    CPC classification number: H01L23/5384 ,  H01L21/765 ,  H01L21/76283 ,  H01L25/0655 ,  H01L29/0649

    Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

    Semiconductor packages with chiplets coupled to a memory device
    8.
    发明授权
    Semiconductor packages with chiplets coupled to a memory device 有权

    公开(公告)号：US11610862B2

    公开(公告)日：2023-03-21

    申请号：US16147560

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Andrew Collins ,  Jianyong Xie

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528

    Abstract: Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.

    Semiconductor package with through bridge die connections
    9.
    发明授权
    Semiconductor package with through bridge die connections 有权

    公开(公告)号：US10950550B2

    公开(公告)日：2021-03-16

    申请号：US15774306

    申请日：2015-12-22

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Jianyong Xie ,  Kemal Aygun

    IPC: H01L23/12 ,  H01L23/14 ,  H01L23/48 ,  H01L21/4763 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

    Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.

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