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    Short link efficient interconnect circuitry
    31.
    发明授权
    Short link efficient interconnect circuitry 有权

    公开(公告)号：US11356303B2

    公开(公告)日：2022-06-07

    申请号：US17214171

    申请日：2021-03-26

    Applicant: Intel Corporation

    Inventor： Hsinho Wu ,  Masashi Shimanouchi ,  Peng Li

    IPC: H04J14/02 ,  H04L25/03 ,  H04L25/14 ,  G06N20/00 ,  H03H21/00

    Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

    Short Link Efficient Interconnect Circuitry
    32.
    发明申请
    Short Link Efficient Interconnect Circuitry 有权

    公开(公告)号：US20210218603A1

    公开(公告)日：2021-07-15

    申请号：US17214171

    申请日：2021-03-26

    Applicant: Intel Corporation

    Inventor： Hsinho Wu ,  Masashi Shimanouchi ,  Peng Li

    IPC: H04L25/03 ,  H04L25/14

    Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

    Concept for storing file system metadata within solid-stage storage devices
    33.
    发明授权
    Concept for storing file system metadata within solid-stage storage devices 有权

    公开(公告)号：US11010079B2

    公开(公告)日：2021-05-18

    申请号：US16378606

    申请日：2019-04-09

    Applicant: Intel Corporation

    Inventor： Peng Li

    IPC: G06F3/06 ,  G06F16/14

    Abstract: Examples relate to a controller apparatus or controller device for a solid-stage storage device, to an apparatus or device for a host computer, to corresponding methods and computer programs, to a solid-stage storage device and to a host computer comprising a solid-state storage device. Examples provide a controller apparatus for a solid-state storage device. The solid-state storage device comprises non-volatile buffer memory circuitry and storage circuitry. The controller apparatus comprises interface circuitry for communicating with a host computer. The controller apparatus comprises processing circuitry configured to obtain a control instruction related to a file system of a partition from the host computer. The partition is at least partially stored within the storage circuitry of the solid-state storage device. The control instruction indicates a location of file system metadata within the partition. The processing circuitry is configured to store the file system metadata within the non-volatile buffer memory circuitry of the solid-state storage device based on the location of the file system metadata.

    Short link efficient interconnect circuitry
    35.
    发明授权
    Short link efficient interconnect circuitry 有权

    公开(公告)号：US10965501B2

    公开(公告)日：2021-03-30

    申请号：US16736436

    申请日：2020-01-07

    Applicant: Intel Corporation

    Inventor： Hsinho Wu ,  Masashi Shimanouchi ,  Peng Li

    IPC: H03H21/00 ,  H04L25/03 ,  H04L25/14 ,  G06N20/00

    Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

    MICROELECTRONIC ASSEMBLIES INCLUDING A THERMAL INTERFACE MATERIAL
    38.
    发明申请
    MICROELECTRONIC ASSEMBLIES INCLUDING A THERMAL INTERFACE MATERIAL 审中-公开

    公开(公告)号：US20200006192A1

    公开(公告)日：2020-01-02

    申请号：US16019899

    申请日：2018-06-27

    Applicant: Intel Corporation

    Inventor： Peng Li ,  Sergio Antonio Chan Arguedas ,  Yongmei Liu ,  Deepak Goyal ,  Ken Hackenberg

    IPC: H01L23/42 ,  H01L23/373 ,  H01L23/367

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the second surface of the package substrate; a cooling apparatus thermally coupled to the second surface of the die; and a thermal interface material (TIM) between the second surface of the die and the cooling apparatus, wherein the TIM includes an indium alloy having a liquidus temperature equal to or greater than about 245 degrees Celsius.

    METHOD AND APPARATUS FOR PERFORMING MULTI-OBJECT TRANSFORMATIONS ON A STORAGE DEVICE
    40.
    发明申请
    METHOD AND APPARATUS FOR PERFORMING MULTI-OBJECT TRANSFORMATIONS ON A STORAGE DEVICE 审中-公开

    公开(公告)号：US20190004737A1

    公开(公告)日：2019-01-03

    申请号：US15639838

    申请日：2017-06-30

    Applicant: INTEL CORPORATION

    Inventor： Jawad Basit Khan ,  Peng Li ,  Sanjeev Trika

    IPC: G06F3/06

    Abstract: In one embodiment, a storage device comprises non-volatile storage media; a controller to receive, from a host, an object definition command that identifies a first data object and a second data object and a transformation to apply to the first data object and the second data object to generate a first transformed object and store the first transformed object in the non-volatile storage media; and a transformation engine to apply the transformation to the first data object and the second data object.

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