公开(公告)号：US11791237B2

公开(公告)日：2023-10-17

申请号：US16019899

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Peng Li ,  Sergio Antonio Chan Arguedas ,  Yongmei Liu ,  Deepak Goyal ,  Ken Hackenberg

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/373 ,  H01L23/00

CPC classification number: H01L23/42 ,  H01L23/367 ,  H01L23/373 ,  H01L23/3736 ,  H01L24/29

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the second surface of the package substrate; a cooling apparatus thermally coupled to the second surface of the die; and a thermal interface material (TIM) between the second surface of the die and the cooling apparatus, wherein the TIM includes an indium alloy having a liquidus temperature equal to or greater than about 245 degrees Celsius.

公开(公告)号：US11226353B2

公开(公告)日：2022-01-18

申请号：US16493503

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Chengqing Hu ,  Mayue Xie ,  Simranjit S. Khalsa ,  Deepak Goyal

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/11 ,  G01R31/28

Abstract: An electrical characterization and fault isolation probe can include a cable, a connector, and a coating over a portion of the cable. The cable can have a first conductor having a first impedance, a second conductor having a second impedance, and a dielectric surrounding the first conductor and electrically isolating the first conductor from the second conductor. The connector can physically couple to, and be in electrical communication with, the cable. The connector can include a first electrical communication pathway and a second electrical communication pathway. The first electrical communication pathway can be electrically isolated from the second electrical communication pathway. The first electrical communication pathway can be in electrical communication with the first conductor. The second electrical communication pathway can be in electrical communication with the second conductor. The connector can have a fifth impedance.

公开(公告)号：US20210407833A1

公开(公告)日：2021-12-30

申请号：US16911466

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Chandrashekara Shashank Kaira ,  Phillip C. Miller ,  Purushotham Kaushik Muthur Srinath ,  Deepak Goyal

IPC: H01L21/67 ,  G01J5/00

Abstract: According to the various examples, a fully integrated system and method for failure analysis using RF-based thermometry enable the detection and location of defects and failures in complex semiconductor packaging architectures. The system provides synchronous amplified RF signals to generate unique thermal signatures at defect locations based on dielectric relaxation loss and heating.

公开(公告)号：US20210364474A1

公开(公告)日：2021-11-25

申请号：US16881025

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Mario Pacheco ,  Odissei Touzanov ,  Jacob Woolsey ,  Deepak Goyal

IPC: G01N29/22 ,  G01R31/28 ,  G01N29/04

Abstract: According to various examples, a method for non-destructive detection of defects in a semiconductor die is described. The method may include positioning an emitter above the semiconductor die. The method may include generating an emitted wave using the emitter that is directed to a focal point on a surface of the die. The method may include generating a reflected wave from the focal point. The focal point may act as a point source reflecting the emitted wave. The method may include positioning a receiver above the die to receive the reflected wave. The method may also include measuring the reflected wave to detect modulations in amplitude in the reflected wave.

公开(公告)号：US20210132113A1

公开(公告)日：2021-05-06

申请号：US16493503

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Chengqing Hu ,  Mayue Xie ,  Simranjit S. Khalsa ,  Deepak Goyal

IPC: G01R1/067 ,  G01R31/28

Abstract: An electrical characterization and fault isolation probe can include a cable, a connector, and a coating over a portion of the cable. The cable can have a first conductor having a first impedance, a second conductor having a second impedance, and a dielectric surrounding the first conductor and electrically isolating the first conductor from the second conductor. The connector can physically couple to, and be in electrical communication with, the cable. The connector can include a first electrical communication pathway and a second electrical communication pathway. The first electrical communication pathway can be electrically isolated from the second electrical communication pathway. The first electrical communication pathway can be in electrical communication with the first conductor. The second electrical communication pathway can be in electrical communication with the second conductor. The connector can have a fifth impedance.

公开(公告)号：US10361167B2

公开(公告)日：2019-07-23

申请号：US15762837

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Pilin Liu ,  Purushotham Kaushik Muthur Srinath ,  Deepak Goyal

IPC: H01L23/00 ,  H01L23/48 ,  B23K35/26 ,  B23K35/02 ,  H01L21/768

Abstract: Some forms relate to an electronic assembly includes a first substrate that has a copper pad mounted to the first substrate. The electronic assembly further includes a second substrate that includes a copper redistribution layer mounted on the second substrate. The electronic assembly further includes bismuth-rich solder that includes 10-40 w.t. % tin. The bismuth-rich solder is electrically engaged with the copper pad and the copper redistribution layer. In some forms, the copper redistribution layer is another copper pad. The first substrate may include a memory die and the second substrate may include a logic die. In other forms, the first and second substrates may be part of a variety of different electronic components. The types of electronic components that are associated with the first and second substrates will depend on part on the application where the electronic assembly is be utilized (among other factors).

公开(公告)号：US09508610B2

公开(公告)日：2016-11-29

申请号：US14499120

申请日：2014-09-27

Applicant: INTEL CORPORATION

Inventor： Shuhong Liu ,  Nilanjan Z. Ghosh ,  Zhiyong Wang ,  Deepak Goyal ,  Shripad Gokhale ,  Jieping Zhang

IPC: H01L21/66 ,  G01B11/06 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L22/12 ,  G01B11/06 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/37001 ,  H01L2224/81

Abstract: A method including emitting a terahertz beam from a light source at a layer of molding material; detecting a reflectance of the beam; and determining a thickness of the layer of molding material. A system including a panel supporter operable to support a panel including a plurality of substrates arranged in a planar array; a light source operable to emit a terahertz beam at a panel on the panel supporter; a detector operable to detect a reflection of a terahertz beam emitted at a panel; and a processor operable to determine a thickness of a material on the panel based on a time delay for an emitted terahertz beam to be detected by the detector.

Abstract translation: 一种包括在成型材料层从光源发射太赫兹光束的方法; 检测光束的反射率; 并确定成型材料层的厚度。 一种包括面板支撑件的系统，其可操作以支撑包括布置在平面阵列中的多个基板的面板; 光源，其可操作以在所述面板支撑件上的面板处发射太赫兹光束; 检测器，用于检测在面板上发射的太赫兹波束的反射; 以及处理器，其可操作以基于由检测器检测的发射的太赫兹光束的时间延迟来确定面板上的材料的厚度。

公开(公告)号：US11506709B2

公开(公告)日：2022-11-22

申请号：US16199092

申请日：2018-11-23

Applicant: Intel Corporation

Inventor： Mario Pacheco ,  Deepak Goyal

IPC: G01N23/04 ,  G01R31/303

Abstract: Embodiments may relate an x-ray filter. The x-ray filter may be configured to be positioned between an x-ray source output and a device under test (DUT) that is to be x-rayed. The x-ray filter may include at least 80% titanium (Ti) by weight. Other embodiments may be described or claimed.

公开(公告)号：US11346818B2

公开(公告)日：2022-05-31

申请号：US16881025

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Mario Pacheco ,  Odissei Touzanov ,  Jacob Woolsey ,  Deepak Goyal

IPC: G01R31/28 ,  G01N29/22 ,  G01N29/04

Abstract: According to various examples, a method for non-destructive detection of defects in a semiconductor die is described. The method may include positioning an emitter above the semiconductor die. The method may include generating an emitted wave using the emitter that is directed to a focal point on a surface of the die. The method may include generating a reflected wave from the focal point. The focal point may act as a point source reflecting the emitted wave. The method may include positioning a receiver above the die to receive the reflected wave. The method may also include measuring the reflected wave to detect modulations in amplitude in the reflected wave.

公开(公告)号：US20190293708A1

公开(公告)日：2019-09-26

申请号：US16302555

申请日：2016-05-17

Applicant: Intel Corporation

Inventor： Mayue Xie ,  Chengqing Hu ,  Jong-Ru Guo ,  Zuoguo Wu ,  Deepak Goyal

IPC: G01R31/28 ,  G01R31/11

Abstract: Disclosed herein are systems and methods for the characterization of transmission media, among other embodiments. For example, a system for characterizing a transmission medium may include: a waveform generator to generate an initial input waveform; waveform pre-processing circuitry to process the initial waveform to generate a processed input waveform for provision to the transmission medium, wherein the processed input waveform has a maximum amplitude greater than a maximum amplitude of the initial input waveform; and waveform output circuitry to display or store data representative of an initial output waveform, wherein the initial output waveform is output from the transmission medium as a reflection or transmission of the processed input waveform.