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    Short-term memory using neuromorphic hardware
    31.
    发明授权
    Short-term memory using neuromorphic hardware 有权

    公开(公告)号：US10733500B2

    公开(公告)日：2020-08-04

    申请号：US14919695

    申请日：2015-10-21

    申请人： International Business Machines Corporation

    发明人： Alexander Andreopoulos ,  Andrew S. Cassidy

    IPC分类号： G06N3/04 ,  G06N3/063

    摘要： In one embodiment, a system includes one or more electronic neurons and one or more electronic axons. Each neuron is connected to at least one electronic axon via an electronic synapse, and at least one of the one or more electronic neurons is configured to store information in a membrane potential thereof and/or at least one of the one or more electronic axons is configured to store information in an axon delay buffer thereof to act as a memory. In another embodiment, a computer-implemented method includes storing information to a memory comprising electronic neurons and electronic axons. Information is stored in either a membrane potential of at least one of the electronic neurons or in an axon delay buffer of at least one of the electronic axons. Also, each neuron is connected to at least one electronic axon via an electronic synapse.

    DYNAMIC MULTISCALE ROUTING ON NETWORKS OF NEUROSYNAPTIC CORES
    35.
    发明申请
    DYNAMIC MULTISCALE ROUTING ON NETWORKS OF NEUROSYNAPTIC CORES 审中-公开

    公开(公告)号：US20180204114A1

    公开(公告)日：2018-07-19

    申请号：US15406211

    申请日：2017-01-13

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Alexander Andreopoulos

    IPC分类号： G06N3/063 ,  G06N3/08 ,  G06N3/04

    CPC分类号： G06N3/049 ,  G06N3/0454 ,  G06N3/063

    摘要： Dynamic multiscale routing on networks of neurosynaptic cores with a feedback attention beam and short term memory with inhibition of return is provided. In various embodiments, an input topographic map is received at a spiking neuromorphic hardware system. A saliency map is received, associating a saliency value with each of a plurality of regions of the input topographic map. Based on the saliency map, a first of the plurality of regions in order of saliency value is routed. The first of the plurality of regions is suppressed. Based on the saliency map, a predetermined number of the plurality of regions are sequentially routed in order of saliency value.

    DYNAMIC GATING USING NEUROMORPHIC HARDWARE
    36.
    发明申请
    DYNAMIC GATING USING NEUROMORPHIC HARDWARE 审中-公开

    公开(公告)号：US20180204109A1

    公开(公告)日：2018-07-19

    申请号：US15405824

    申请日：2017-01-13

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Alexander Andreopoulos

    IPC分类号： G06N3/04 ,  G06N3/08

    CPC分类号： G06N3/063 ,  G06N3/049

    摘要： Dynamic gating for neuromorphic systems and the configuration thereof are provided. In various embodiments, neurosynaptic system comprises a neurosynaptic core. The neuromorphic core comprises a plurality of neurons and axons. The neurosynaptic core comprises a programmable gate operative to receive a control signal and selectively output a first output signal based on the control signal. In various embodiments, a plurality of input parameters are read, defining the behavior of a programmable gate. Based upon the plurality of input parameters, a neurosynaptic core is configured to provide a programmable gate operative to receive a control signal and selectively output a first output signal based on the control signal.

    SHORT-TERM MEMORY USING NEUROMORPHIC HARDWARE
    38.
    发明申请
    SHORT-TERM MEMORY USING NEUROMORPHIC HARDWARE 审中-公开

    公开(公告)号：US20170116513A1

    公开(公告)日：2017-04-27

    申请号：US14919695

    申请日：2015-10-21

    申请人： International Business Machines Corporation

    发明人： Alexander Andreopoulos ,  Andrew S. Cassidy

    IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08

    CPC分类号： G06N3/0445 ,  G06N3/049 ,  G06N3/063

    摘要： In one embodiment, a system includes one or more electronic neurons and one or more electronic axons. Each neuron is connected to at least one electronic axon via an electronic synapse, and at least one of the one or more electronic neurons is configured to store information in a membrane potential thereof and/or at least one of the one or more electronic axons is configured to store information in an axon delay buffer thereof to act as a memory. In another embodiment, a computer-implemented method includes storing information to a memory comprising electronic neurons and electronic axons. Information is stored in either a membrane potential of at least one of the electronic neurons or in an axon delay buffer of at least one of the electronic axons. Also, each neuron is connected to at least one electronic axon via an electronic synapse.

    Low spike count ring buffer mechanism on neuromorphic hardware
    40.
    发明授权
    Low spike count ring buffer mechanism on neuromorphic hardware 有权

    公开(公告)号：US11537855B2

    公开(公告)日：2022-12-27

    申请号：US16140269

    申请日：2018-09-24

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Alexander Andreopoulos

    IPC分类号： G06N3/06 ,  G06N3/04 ,  G11C11/54

    摘要： Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.